Abstract: A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and the p-type substrate are coupled to ground. The various polarities can be reversed in another embodiment.

Abstract: A non-volatile memory cell with increased charge retention is fabricated on the same substrate as logic devices using a single-gate conventional logic process. A silicide-blocking dielectric structure is formed over a floating gate of the NVM cell, thereby preventing silicide formation over the floating gate, while allowing silicide formation over the logic devices. Silicide spiking and bridging are prevented in the NVM cell, as silicide-blocking dielectric structure prevents silicide metal from coming in contact with the floating gate or adjacent sidewall spacers. The silicide-blocking dielectric layer may expose portions of the active regions of the NVM cell, away from the floating gate and adjacent sidewall spacers, thereby enabling silicide formation on these portions. Alternately, the silicide-blocking dielectric layer may cover the active regions of the NVM cell during silicide formation. In this case, silicide-blocking dielectric layer may be thinned or removed after silicide formation.

Abstract: A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and the p-type substrate are coupled to ground. The various polarities can be reversed in another embodiment.

Abstract: A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).

Abstract: A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.

Abstract: A method and apparatus for scaling an embedded DRAM array from a first process to a second process, wherein the scaling involves reducing the linear dimensions of features by a constant scale factor. From the first process to the second process, DRAM cell capacitor layout area is reduced by the square of the scale factor, while cell capacitance is reduced by the scale factor. The voltage used to supply the logic transistors is scaled down from the first process to the second process. However, the voltage used to supply the sense amplifiers remains constant in both processes. Thus, in an embedded DRAM array of the second process, sense amplifiers are supplied by a greater voltage than the logic transistors. This allows the sensing voltage of DRAM cells to be maintained from one process generation to another, while allowing memory size to scale with the square of the process scale factor.

Abstract: A word line driver is provided for accessing a DRAM cell embedded in a conventional logic process. The DRAM cell includes a p-channel access transistor coupled to a cell capacitor. The word line driver includes an n-channel transistor located in a p-well, wherein the p-well is located in a deep n-well. The deep n-well is located in a p-type substrate. A word line couples the drain of the n-channel transistor to the gate of the p-channel access transistor. A negative boosted voltage supply applies a negative boosted voltage to the p-well and the source of the n-channel transistor. The negative boosted voltage is less than ground by an amount equal to or greater than the threshold voltage of the p-channel access transistor. The deep n-well and the p-type substrate are coupled to ground. The various polarities can be reversed in another embodiment.

Abstract: Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.

Abstract: A high-speed partial-word write operation is performed in a memory system. First, an error correction code (ECC) word, which includes a data word and associated error correction bits, is read from a memory array. A word line and a plurality of sense amplifiers are enabled during this read operation. The read data word is corrected in response to the associated error correction bits, thereby creating a corrected data word. The corrected data word is merged with a write data word, thereby creating a merged write data word. Write error correction bits are generated in response to the merged write data word, and the merged write data word and write error correction bits are written to the memory array. The word line and the plurality of sense amplifiers remain enabled from the reading operation through the write operation, thereby speeding up the partial-word write operation.

Abstract: A memory device that uses error correction code (ECC) circuitry to improve the reliability of the memory device in view of single-bit errors caused by hard failure or soft error. A write buffer is used to post write data, so that ECC generation and memory write array operation can be carried out in parallel. As a result there is no penalty in write latency or memory cycle time due to ECC generation. A write-back buffer is used to post corrected ECC words during read operations, so that write-back of corrected ECC words does not need to take place during the same cycle that data is read. Instead, write-back operations are performed during idle cycles when no external memory access is requested, such that the write back operation does not impose a penalty on memory cycle time or affect memory access latency.

Abstract: A memory system is provided that includes an array of memory cells that require periodic refresh, and a temperature-adaptive refresh controller. Data retention time of the memory cells decreases exponentially as temperature increases. The temperature-adaptive refresh controller selects the refresh period of the memory cells in response to the subthreshold current of a reference transistor. The subthreshold current of the reference transistor increases exponentially as temperature increases As a result, the refresh period is empirically tied to the data retention time. Consequently, the power required for refresh operations decreases as temperature decreases. Power is therefore conserved in applications that operate predominantly at room temperature.

Abstract: A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.

Abstract: A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.

Abstract: A non-volatile memory (NVM) system includes a NVM cell having: a semiconductor region having a first conductivity type; a gate dielectric layer located over the semiconductor region; a gate electrode located over the gate dielectric layer; a source region and a drain region of a second conductivity type, opposite the first conductivity type, located in the semiconductor region and aligned with the gate electrode; a crown electrode having a base that contacts the gate electrode and walls that extend vertically from the base region, away from the gate electrode; a dielectric layer located over the crown electrode, wherein the dielectric layer extends over at least interior surfaces of the walls; and a plate electrode located over the dielectric layer, wherein the plate electrode extends over at least interior surfaces of the walls.

Abstract: An array of memory cells that require periodic refresh is operated in a single-cell mode during normal operating conditions. Upon receiving an asserted standby control signal from an accessing memory client, the array enters a standby mode from the normal operating conditions. The standby mode can be specified as a differential-cell mode, a single-cell mode or a non-retentive mode. To enter the differential-cell standby mode, data stored in the single-cell mode is converted to a differential-cell mode. In this conversion, half of the data stored in the single-cell mode is saved, while the other half is discarded. In the differential-cell standby mode, refresh operations are performed less frequently than in the normal operating mode, thereby conserving power. The external clock signal provided by the accessing memory client can be disabled during the differential-cell standby mode, as a local clock signal is provided to implement the refresh operations during standby mode.

Abstract: An array of memory cells that require periodic refresh is operated in a single-cell mode during normal operating conditions. Upon receiving an asserted standby control signal from an accessing memory client, the array enters a standby mode from the normal operating conditions. The standby mode can be specified as a differential-cell mode, a single-cell mode or a non-retentive mode. To enter the differential-cell standby mode, data stored in the single-cell mode is converted to a differential-cell mode. In this conversion, half of the data stored in the single-cell mode is saved, while the other half is discarded. In the differential-cell standby mode, refresh operations are performed less frequently than in the normal operating mode, thereby conserving power. The external clock signal provided by the accessing memory client can be disabled during the differential-cell standby mode, as a local clock signal is provided to implement the refresh operations during standby mode.

Abstract: A memory system that includes a DRAM cell that includes an access transistor and a storage capacitor. The storage capacitor is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. Subsequently, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide.

Abstract: Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.

Abstract: A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing client. The method and apparatus handles external accesses and refresh operations such that the refresh operations do not interfere with the external accesses under any conditions. As a result, an SRAM compatible device can be built from DRAM or 1-Transistor cells. A clock division scheme is implemented to perform external accesses during one portion of a clock cycle, and required refresh operations during another portion of the same clock cycle.

Abstract: A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.