Patents by Inventor Won Je Park
Won Je Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11940845Abstract: A display device includes a display panel which includes a display area and a non-display area, a plurality of signal wirings arranged in the display area, a plurality of fanout wirings arranged in the non-display area and electrically connected to the signal wirings, and a plurality of connecting wirings connecting the signal wirings to the fanout wirings, where some of the plurality of fanout wirings intersect and are overlapped with each other in a plan view.Type: GrantFiled: April 10, 2023Date of Patent: March 26, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Ki Ho Bang, Hwa Jeong Kim, Yong Hwan Park, Yong Je Jeon, Won Suk Choi
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Publication number: 20240096921Abstract: A semiconductor device includes a first stacked structure including a first substrate having unit pixels, and a first interconnect layer having first conductive lines connected to the unit pixels; a second stacked structure including a second substrate having first circuit elements configured to operate the unit pixels and a second interconnect layer having second conductive lines connected to the first circuit elements and an electrode pad, and a first interconnection via structure penetrating the second substrate; a third stacked structure including a third substrate having second circuit elements configured to process signals received from the second stacked structure, and a third interconnect layer having third conductive lines connected to the second circuit elements; and a pad open region disposed outside of a pixel region including the unit pixels and exposing a top surface of the electrode pad to outside.Type: ApplicationFiled: September 15, 2023Publication date: March 21, 2024Inventor: Won Je PARK
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Publication number: 20230133670Abstract: This patent document discloses embodiments of image sensing devices including, an image sensing device which includes a substrate including a substrate surface and a trench extending from the substrate surface, a plurality of photoelectric conversion elements formed in the substrate and operable to convert incident light into photocharge, an electrode formed in the trench and configured to receive a bias voltage for suppressing a dark current, and a light blocking layer formed over the substrate surface of the substrate to block light from transmitting therethrough, and configured to be electrically conductive to receive the bias voltage and transmit the received bias voltage to the electrode.Type: ApplicationFiled: November 1, 2022Publication date: May 4, 2023Inventors: Kyoung In LEE, Won Je PARK, Byoung Gyu KIM
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Patent number: 8624310Abstract: A method of fabricating an image sensor may include providing a substrate including light-receiving and non-light-receiving regions; forming a plurality of gates on the non-light-receiving region; ion-implanting a first-conductivity-type dopant into the light-receiving region to form a first dopant region of a pinned photodiode; primarily ion-implanting a second-conductivity-type dopant, different from the first-conductivity-type dopant, into an entire surface of the substrate, using the gates as a first mask; forming spacers on both side walls of the gates; and secondarily ion-implanting the second-conductivity-type dopant into the entire surface of the substrate, using the plurality of gates including the spacers as a second mask, to complete a second dopant region of the pinned photodiode.Type: GrantFiled: March 9, 2011Date of Patent: January 7, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Won-je Park, Chan Park, Young-hoon Park, Jae-ho Song, Jong-wook Hong, Keo-sung Park
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Patent number: 8354292Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.Type: GrantFiled: March 6, 2012Date of Patent: January 15, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Patent number: 8309996Abstract: Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and methods of manufacturing the same are provided, the sensors include an epitaxial layer on a substrate in which a first, second, third and fourth region are defined. A photodiode may be formed at an upper portion of the epitaxial layer in the first region. A plurality of gate structures may be formed on the epitaxial layer in the second, third and fourth regions. A first blocking layer may be formed on the gate structures and the epitaxial layer in the first and second regions. A first impurity layer may be formed at an upper portion of the epitaxial layer adjacent to the gate structures in the second region, and a second impurity layer at upper portions of the epitaxial layer adjacent to the gate structures in the third and fourth regions. A color filter layer may be formed over the photodiode. A microlens may be formed on the color filter layer.Type: GrantFiled: March 16, 2011Date of Patent: November 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Ui-Sik Kim, Young-Hoon Park, Won-Je Park, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Publication number: 20120164783Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.Type: ApplicationFiled: March 6, 2012Publication date: June 28, 2012Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Patent number: 8143142Abstract: A method of fabricating an epi-wafer includes providing a wafer including boron by cutting a single crystal silicon ingot, growing an insulating layer on one surface of the wafer, performing thermal treatment of the wafer, removing the insulating layer formed on one surface of the wafer, mirror-surface-grinding one surface of the wafer, and growing an epitaxial layer on one surface of the wafer and forming a high-density boron layer within the wafer that corresponds to the interface between the wafer and the epitaxial layer.Type: GrantFiled: March 15, 2010Date of Patent: March 27, 2012Assignee: SAMSUNG Electronics Co., Ltd.Inventors: Young-Soo Park, Gi-Jung Kim, Won-Je Park, Jae-Sik Bae
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Patent number: 8138530Abstract: In a method of manufacturing a CMOS image sensor, a P type epitaxial layer is formed on an N type substrate. A deep P+ type well layer is formed in the P type epitaxial layer. An N type deep guardring well is formed in a photodiode guardring region. The N type deep guardring region makes contact with the N type substrate and also be connected with an operational voltage terminal. A triple well is formed in a photodiode region and a peripheral circuit region. The triple well is used for forming a PMOS and an NMOS having different operational voltages. An isolation region is formed in the photodiode region. The isolation region in the photodiode region has a depth different from a depth of an isolation region in the peripheral circuit region.Type: GrantFiled: June 11, 2009Date of Patent: March 20, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Won-Je Park, Young-Hoon Park, Ui-Sik Kim, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Keang
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Publication number: 20120001241Abstract: A CMOS image sensor (CIS) for sensing visible light and infrared (IR) light, capable of effectively preventing increase in electrical crosstalk that is caused when photodiodes are formed deeply and the thickness of an epitaxial layer is increased due to deep permeation of IR light, and a method of fabricating the CIS. The CIS includes a substrate; the PNP triple layer including a P-type lower layer, an N-type intermediate layer, and a P-type upper layer that are sequentially stacked on the substrate; a plurality of photodiodes formed in the P-type upper layer and isolated from each other by isolation regions; a wiring layer formed on the P-type upper layer and the plurality of photodiodes and including a plurality of wirings; and a plurality of lenses for focusing light to transfer the light to the photodiodes.Type: ApplicationFiled: June 15, 2011Publication date: January 5, 2012Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: Won-je Park
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Publication number: 20110204468Abstract: Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning the gate insulating film and the gate conductive film; and fabricating a transfer gate electrode by forming a first-conductive-type photodiode in the semiconductor substrate adjacent to one region of the transfer gate pattern, by forming a second-conductive-type photodiode on the first-conductive-type photodiode, and by forming a first-conductive-type floating diffusion region in the semiconductor substrate adjacent to the other region of the transfer gate pattern.Type: ApplicationFiled: April 26, 2011Publication date: August 25, 2011Inventors: Jae-ho Song, Chan Park, Young-hoon Park, Sang-il Jung, Jong-wook Hong, Keo-sung Park, Eun-soo Kim, Won-je Park, Jin-Hyeong Park, Dae-cheol Seong, Won-jeong Lee, Pu-ra Kim
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Patent number: 7994551Abstract: An image sensor according to an example embodiment may include a plurality of photoelectric transformation active regions, a plurality of read active regions, and/or at least one read gate. The plurality of photoelectric transformation active regions may be formed on a substrate. Each read active region may be formed adjacent to one of the plurality of photoelectric transformation active regions. Each read gate may be formed on one of the read active regions and partially overlap at least one of the adjacent photoelectric transformation active regions. Each read gate may be electrically isolated from the overlapping portion of the photoelectric transformation active region.Type: GrantFiled: September 7, 2007Date of Patent: August 9, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Won-je Park, Duk-min Yi
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Publication number: 20110163362Abstract: A method of fabricating an image sensor may include providing a substrate including light-receiving and non-light-receiving regions; forming a plurality of gates on the non-light-receiving region; ion-implanting a first-conductivity-type dopant into the light-receiving region to form a first dopant region of a pinned photodiode; primarily ion-implanting a second-conductivity-type dopant, different from the first-conductivity-type dopant, into an entire surface of the substrate, using the gates as a first mask; forming spacers on both side walls of the gates; and secondarily ion-implanting the second-conductivity-type dopant into the entire surface of the substrate, using the plurality of gates including the spacers as a second mask, to complete a second dopant region of the pinned photodiode.Type: ApplicationFiled: March 9, 2011Publication date: July 7, 2011Inventors: Won-je Park, Chan Park, Young-hoon Park, Jae-ho Song, Jong-wook Hong, Keo-sung Park
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Publication number: 20110163363Abstract: Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and methods of manufacturing the same are provided, the sensors include an epitaxial layer on a substrate in which a first, second, third and fourth region are defined. A photodiode may be formed at an upper portion of the epitaxial layer in the first region. A plurality of gate structures may be formed on the epitaxial layer in the second, third and fourth regions. A first blocking layer may be formed on the gate structures and the epitaxial layer in the first and second regions. A first impurity layer may be formed at an upper portion of the epitaxial layer adjacent to the gate structures in the second region, and a second impurity layer at upper portions of the epitaxial layer adjacent to the gate structures in the third and fourth regions. A color filter layer may be formed over the photodiode. A microlens may be formed on the color filter layer.Type: ApplicationFiled: March 16, 2011Publication date: July 7, 2011Inventors: Ui-Sik Kim, Young-Hoon Park, Won-Je Park, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Patent number: 7973346Abstract: Disclosed is a image sensor (e.g., a CMOS image sensor) including pixels each having a transfer transistor and a drive transistor, in which the gate of at least one of the transistors has a boosting gate disposed over it comprised of a conductive film pattern with interposing an insulation film. Thus, a voltage applied to the boosting gate is capacitively coupled to at least one of the transfer gate of the transfer transistor and a drive gate of the drive transistor. The transfer gate is supplied with the sum of the transfer voltage and the boosting gate-coupling voltage as a result and there is no need for providing a high voltage generator for the image sensor. The dynamic range of operation may be enhanced if such a coupling voltage is applied to the drive gate of the drive transistor.Type: GrantFiled: January 18, 2006Date of Patent: July 5, 2011Assignee: Samsung Electronic Co., Ltd.Inventors: Young-Hoon Park, Won-Je Park, Tae-Seok Oh, Jae-Ho Song
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Patent number: 7955924Abstract: Example embodiments disclose an image sensor capable of preventing or reducing image lag and a method of manufacturing the same. Example methods may include forming a gate insulating film and a gate conductive film doped with a first-conductive-type dopant on a semiconductor substrate; forming a transfer gate pattern by patterning the gate insulating film and the gate conductive film; and fabricating a transfer gate electrode by forming a first-conductive-type photodiode in the semiconductor substrate adjacent to one region of the transfer gate pattern, by forming a second-conductive-type photodiode on the first-conductive-type photodiode, and by forming a first-conductive-type floating diffusion region in the semiconductor substrate adjacent to the other region of the transfer gate pattern.Type: GrantFiled: January 10, 2007Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-ho Song, Chan Park, Young-hoon Park, Sang-il Jung, Jong-wook Hong, Keo-sung Park, Eun-soo Kim, Won-je Park, Jin-Hyeong Park, Dae-cheol Seong, Won-jeong Lee, Pu-ra Kim
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Patent number: 7932120Abstract: Complementary metal-oxide semiconductor (CMOS) image sensors (CIS) and methods of manufacturing the same are provided, the sensors include an epitaxial layer on a substrate in which a first, second, third and fourth region are defined. A photodiode may be formed at an upper portion of the epitaxial layer in the first region. A plurality of gate structures may be formed on the epitaxial layer in the second, third and fourth regions. A first blocking layer may be formed on the gate structures and the epitaxial layer in the first and second regions. A first impurity layer may be formed at an upper portion of the epitaxial layer adjacent to the gate structures in the second region, and a second impurity layer at upper portions of the epitaxial layer adjacent to the gate structures in the third and fourth regions. A color filter layer may be formed over the photodiode. A microlens may be formed on the color filter layer.Type: GrantFiled: August 27, 2009Date of Patent: April 26, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Ui-Sik Kim, Young-Hoon Park, Won-Je Park, Dae-Cheol Seong, Yeo-Ju Yoon, Bo-Bae Kang
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Patent number: 7927902Abstract: A method of fabricating an image sensor may include providing a substrate including light-receiving and non-light-receiving regions; forming a plurality of gates on the non-light-receiving region; ion-implanting a first-conductivity-type dopant into the light-receiving region to form a first dopant region of a pinned photodiode; primarily ion-implanting a second-conductivity-type dopant, different from the first-conductivity-type dopant, into an entire surface of the substrate, using the gates as a first mask; forming spacers on both side walls of the gates; and secondarily ion-implanting the second-conductivity-type dopant into the entire surface of the substrate, using the plurality of gates including the spacers as a second mask, to complete a second dopant region of the pinned photodiode.Type: GrantFiled: May 16, 2007Date of Patent: April 19, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Won-je Park, Chan Park, Young-hoon Park, Jae-ho Song, Jong-wook Hong, Keo-sung Park
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Patent number: 7875488Abstract: A method of fabricating an image sensor according to example embodiments may include forming a photodiode in a photoelectric conversion region of a substrate and forming an etch stop layer on the substrate. The etch stop layer may be patterned to form an inner lens on the photoelectric conversion region and an etch stop layer pattern on a transistor region of the substrate. A metal interconnection structure may be formed on the inner lens and the etch stop layer pattern. Accordingly, the number of additional processes for fabricating an image sensor may be reduced.Type: GrantFiled: July 31, 2007Date of Patent: January 25, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Wook Hong, Tae-Seok Oh, Duk-Min Yi, Young-Mook Oh, Won-Je Park
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Publication number: 20100233869Abstract: A method of fabricating an epi-wafer includes providing a wafer including boron by cutting a single crystal silicon ingot, growing an insulating layer on one surface of the wafer, performing thermal treatment of the wafer, removing the insulating layer formed on one surface of the wafer, mirror-surface-grinding one surface of the wafer, and growing an epitaxial layer on one surface of the wafer and forming a high-density boron layer within the wafer that corresponds to the interface between the wafer and the epitaxial layer.Type: ApplicationFiled: March 15, 2010Publication date: September 16, 2010Applicant: Samsung Electronics Co., Ltd.Inventors: Young-Soo PARK, Gi-Jung KIM, Won-Je PARK, Jae-Sik BAE