Patents by Inventor Woo-Hyeong Lee
Woo-Hyeong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170170016Abstract: Methods for multiple patterning a substrate may include: forming a hard mask including a carbonaceous layer and an oxynitride layer over the carbonaceous layer on a substrate; and forming a first pattern into the oxynitride layer and partially into the carbonaceous layer using a first soft mask positioned over the hard mask. A wet etching removes a portion of the first soft mask from the first pattern in the oxynitride layer without damaging the carbonaceous layer. Subsequently, a second pattern and a third pattern are formed into the hard mask, creating a multiple pattern in the hard mask. The multiple pattern may be etched into the substrate, followed by removing any remaining portion of the hard mask.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Woo-Hyeong Lee, Jujin An, Shahrukh A. Khan, Rosa A. Orozco-Teran, Oluwafemi O. Ogunsola, William K. Henson, Scott R. Stiffler
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Patent number: 9171758Abstract: Embodiments of the present invention provide an improved method for forming transistor contacts. A sacrificial layer is deposited in a first set of contact cavities, and a capping layer is formed on the sacrificial layer. This protects the first set of contact cavities during formation of a second set of contact cavities. The sacrificial layer is then removed, and the first and second sets of contact cavities are filled with a conductive material.Type: GrantFiled: March 31, 2014Date of Patent: October 27, 2015Assignee: International Business Machines CorporationInventors: Murshed Mahmud Chowdhury, Woo-Hyeong Lee, Aimin Xing
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Publication number: 20150279734Abstract: Embodiments of the present invention provide an improved method for forming transistor contacts. A sacrificial layer is deposited in a first set of contact cavities, and a capping layer is formed on the sacrificial layer. This protects the first set of contact cavities during formation of a second set of contact cavities. The sacrificial layer is then removed, and the first and second sets of contact cavities are filled with a conductive material.Type: ApplicationFiled: March 31, 2014Publication date: October 1, 2015Applicant: International Business Machines CorporationInventors: Murshed Mahmud Chowdhury, Woo-Hyeong Lee, Aimin Xing
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Patent number: 7893493Abstract: An intermediate hybrid surface orientation structure may include a silicon-on-insulator (SOI) substrate adhered to a bulk silicon substrate, the silicon of the SOI substrate having a different surface orientation than that of the bulk silicon substrate, and a reachthrough region extending through the SOI substrate to the bulk silicon substrate, the reachthrough region including a silicon nitride liner over a silicon oxide liner and a silicon epitaxially grown from the bulk silicon substrate, the epitaxially grown silicon extending into an undercut into the silicon oxide liner under the silicon nitride liner, wherein the epitaxially grown silicon is substantially stacking fault free.Type: GrantFiled: July 10, 2006Date of Patent: February 22, 2011Assignees: International Business Machines Corproation, Advanced Micro Devices, Inc.Inventors: Yun-Yu Wang, Linda Black, Judson R. Holt, Woo-Hyeong Lee, Scott Luning, Christopher D. Sheraw
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Patent number: 7851376Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.Type: GrantFiled: February 2, 2009Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Daewon Yang, Woo-Hyeong Lee, Tai-chi Su, Yun-Yu Wang
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Patent number: 7790581Abstract: A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.Type: GrantFiled: January 9, 2006Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Byeong Y. Kim, Xiaomeng Chen, Woo-Hyeong Lee, Huilong Zhu
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Patent number: 7776624Abstract: A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atomic percent of a first semiconductor material in the first semiconductor layer is equal to a substrate atomic percent of the substrate semiconductor material in the semiconductor substrate.Type: GrantFiled: July 8, 2008Date of Patent: August 17, 2010Assignee: International Business Machines CorporationInventors: Ashima B. Chakravarti, Judson Robert Holt, Jeremy John Kempisty, Suk Hoon Ku, Woo-Hyeong Lee, Amlan Majumdar, Ryan Matthew Mitchell, Renee Tong Mo, Zhibin Ren, Dinkar Singh
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Patent number: 7682887Abstract: Methods and resulting structure of forming a transistor having a high mobility channel are disclosed. In one embodiment, the method includes providing a gate electrode including a gate material area and a gate dielectric, the gate electrode being positioned over a channel in a silicon substrate. A dielectric layer is formed about the gate electrode, and the gate material area and the gate dielectric are removed from the gate electrode to form an opening into a portion of the silicon substrate that exposes source/drain extensions. A high mobility semiconductor material, i.e., one having a carrier mobility greater than doped silicon, is then formed in the opening such that it laterally contacts the source/drain extensions. The gate dielectric and the gate material area may then be re-formed. This invention eliminates the high temperature steps after the formation of high mobility channel material used in related art methods.Type: GrantFiled: November 8, 2006Date of Patent: March 23, 2010Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Woo-Hyeong Lee
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Patent number: 7674720Abstract: Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.Type: GrantFiled: June 2, 2008Date of Patent: March 9, 2010Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc.Inventors: Yun-Yu Wang, Linda Black, Judson R. Holt, Woo-Hyeong Lee, Scott Luning, Christopher D. Sheraw
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Patent number: 7655557Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: GrantFiled: June 24, 2008Date of Patent: February 2, 2010Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Publication number: 20100009524Abstract: A semiconductor fabrication method. The method includes providing a semiconductor substrate, wherein the semiconductor substrate includes a semiconductor material. Next, a top portion of the semiconductor substrate is removed. Next, a first semiconductor layer is epitaxially grown on the semiconductor substrate, wherein a first atom percent of the semiconductor material in the first semiconductor layer is equal to a certain atom percent of the semiconductor material in the semiconductor substrate.Type: ApplicationFiled: July 8, 2008Publication date: January 14, 2010Applicant: INTERNATIONAL BUSINESS MACHINESInventors: Ashima B. Chakravarti, Judson Robert Holt, Jeremy John Kempisty, Suk Hoon Ku, Woo-Hyeong Lee, Amlan Majumdar, Ryan Matthew Mitchell, Renee Tong Mo, Zhibin Ren, Dinkar Singh
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Publication number: 20090137109Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.Type: ApplicationFiled: February 2, 2009Publication date: May 28, 2009Applicant: International Business Machines CorporationInventors: Daewon Yang, Woo-Hyeong Lee, Tai-chi Su, Yun-Yu Wang
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Patent number: 7514370Abstract: Embodiments of the invention provide a method of forming a compressive stress nitride film overlying a plurality of p-type field effect transistor gate structures produced on a substrate through a high-density plasma deposition process. Embodiments include generating an environment filled with high-density plasma using source gases of at least silane, argon and nitrogen; biasing the substrate to a high frequency power of varying density, in a range between 0.8 W/cm2 and 5.0 W/cm2; and depositing the high-density plasma to the plurality of gate structures to form the compressive stress nitride film.Type: GrantFiled: May 19, 2006Date of Patent: April 7, 2009Assignee: International Business Machines CorporationInventors: Daewon Yang, Woo-Hyeong Lee, Tai-chi Su, Yun-Yu Wang
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Publication number: 20080268609Abstract: Methods are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.Type: ApplicationFiled: June 2, 2008Publication date: October 30, 2008Inventors: Yun-Yu Wang, Linda Black, Judson R. Holt, Woo-Hyeong Lee, Scott Luning, Christopher D. Sheraw
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Patent number: 7439110Abstract: A strained HOT MOSFET fabrication method. The MOSFET fabrication method includes providing a semiconductor structure which includes (a) a first semiconductor layer having a first crystallographic orientation, (b) a buried insulating layer on top of the first semiconductor layer, (c) a second semiconductor layer on top of the buried oxide layer. The second semiconductor layer has a second crystallographic orientation different from the first crystallographic orientation. The method further includes forming a third semiconductor layer on top of the first semiconductor layer which has the first crystallographic orientation. The method further includes forming a fourth semiconductor layer on top of the third semiconductor layer. The fourth semiconductor layer (a) comprises a different material than that of the third semiconductor layer, and (b) has the first crystallographic orientation.Type: GrantFiled: May 19, 2006Date of Patent: October 21, 2008Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Woo-Hyeong Lee, Huilong Zhu
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Publication number: 20080254622Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: ApplicationFiled: June 24, 2008Publication date: October 16, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Publication number: 20080224216Abstract: A strained HOT MOSFET. The MOSFET includes (a) a first semiconductor layer having a first crystallographic orientation; (b) a buried oxide layer on top of the first semiconductor layer; (c) a second semiconductor layer on top of the buried oxide layer, wherein the second semiconductor layer has a second crystallographic orientation, and wherein the second crystallographic orientation is different from the first crystallographic orientation; (d) a third semiconductor layer on top of the first semiconductor layer, wherein the third semiconductor layer has the first crystallographic orientation; and (e) a fourth semiconductor layer on top of the third semiconductor layer, wherein the fourth semiconductor layer includes a different material than that of the third semiconductor layer, and wherein the fourth semiconductor layer has the first crystallographic orientation.Type: ApplicationFiled: May 29, 2008Publication date: September 18, 2008Inventors: Kangguo Cheng, Woo-Hyeong Lee, Huilong Zhu
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Patent number: 7411227Abstract: The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.Type: GrantFiled: April 19, 2006Date of Patent: August 12, 2008Assignee: International Business Machines CorporationInventors: Ricky S. Amos, Diane C. Boyd, Cyril Cabral, Jr., Richard D. Kaplan, Jakub T. Kedzierski, Victor Ku, Woo-Hyeong Lee, Ying Li, Anda C. Mocuta, Vijay Narayanan, An L. Steegen, Maheswaren Surendra
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Publication number: 20080185592Abstract: A pair of semiconductor structures and a method for fabricating a semiconductor structure each utilize a semiconductor substrate having a first crystallographic orientation, and a dielectric layer located thereupon. The method provides for epitaxially growing a semiconductor layer on the semiconductor substrate to encapsulate the dielectric layer. The method also provides for patterning the semiconductor layer to yield a semiconductor structure that comprises a bulk semiconductor structure and a semiconductor-on-insulator structure, or alternatively a patterned semiconductor layer that straddles the dielectric layer and contacts the semiconductor substrate.Type: ApplicationFiled: January 9, 2006Publication date: August 7, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Byeong Y. Kim, Xiaomeng Chen, Woo-Hyeong Lee, Huilong Zhu
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Publication number: 20080006876Abstract: Methods and a structure are disclosed for providing stacking fault reduced epitaxially grown silicon for use in hybrid surface orientation structures. In one embodiment, a method includes depositing a silicon nitride liner over a silicon oxide liner in an opening, etching to remove the silicon oxide liner and silicon nitride liner on a lower surface of the opening, undercutting the silicon nitride liner adjacent to the lower surface, and epitaxially growing silicon in the opening. The silicon is substantially reduced of stacking faults because of the negative slope created by the undercut.Type: ApplicationFiled: July 10, 2006Publication date: January 10, 2008Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, ADVANCED MICRO DEVICES, INC.Inventors: Yun-Yu Wang, Linda Black, Judson R. Holt, Woo-Hyeong Lee, Scott Luning, Christopher D. Sheraw