Abstract: A receiver, an operating method of the receiver, and a beamforming radar system including the receiver are provided. A beamforming receiver may include a demodulation circuit configured to receive a signal reflected from an object via an antenna, to demodulate the received signal, and to generate a demodulated signal, and a time delay circuit configured to generate a digital signal by processing the demodulated signal based on reference clock signals, wherein the digital signal including static delay information associated with a static motion of the object, and dynamic delay information associated with a dynamic motion of the object.

Abstract: A transmitter and a receiver for reducing power consumption in a frequency modulation-ultra-wideband (FM-UWB) communication system are provided. The transmitter includes a detector configured to generate a pulse signal when an edge of a digital signal is detected. The transmitter further includes a first modulator configured to modulate the digital signal into a first modulation signal based on a value of the digital signal. The transmitter further includes a second modulator configured to modulate the first modulation signal into a second modulation signal based on a frequency of the first modulation signal when the pulse signal is generated.

Abstract: An apparatus and method for ultra wideband (UWB) communication, using a dual band pass filter (BPF) is disclosed. The UWB communication apparatus may include a first BPF performing a first band pass filtering with respect to a UWB signal, a second BPF that has a center frequency differing from a center frequency of the first BPF, and performs a second band pass filtering with respect to the UWB signal, a first envelope detector that detects a size of a first signal filtered in the first BPF, a second envelope detector that detects a size of a second signal filtered in the second BPF, and a demodulator that demodulates a UWB signal, using the size of the first signal and the size of the second signal.

Abstract: A receiver, an operating method of the receiver, and a beamforming radar system including the receiver are provided. A beamforming receiver may include a demodulation circuit configured to receive a signal reflected from an object via an antenna, to demodulate the received signal, and to generate a demodulated signal, and a time delay circuit configured to generate a digital signal by processing the demodulated signal based on reference clock signals, wherein the digital signal including static delay information associated with a static motion of the object, and dynamic delay information associated with a dynamic motion of the object.

Abstract: A pulse generation apparatus includes a delay pulse generator configured to generate a plurality of delay pulses, an amplitude modulator configured to modulate amplitudes of the plurality of delay pulses, and a Gaussian pulse generator configured to generate a Gaussian pulse based on the amplitude-modulated delay pulses.

Abstract: An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.

Abstract: A pulse generation apparatus includes a delay pulse generator configured to generate a plurality of delay pulses, an amplitude modulator configured to modulate amplitudes of the plurality of delay pulses, and a Gaussian pulse generator configured to generate a Gaussian pulse based on the amplitude-modulated delay pulses.

Abstract: An apparatus and method for ultra wideband (UWB) communication, using a dual band pass filter (BPF) is disclosed. The UWB communication apparatus may include a first BPF performing a first band pass filtering with respect to a UWB signal, a second BPF that has a center frequency differing from a center frequency of the first BPF, and performs a second band pass filtering with respect to the UWB signal, a first envelope detector that detects a size of a first signal filtered in the first BPF, a second envelope detector that detects a size of a second signal filtered in the second BPF, and a demodulator that demodulates a UWB signal, using the size of the first signal and the size of the second signal.

Abstract: A transmitter and a receiver for reducing power consumption in a frequency modulation-ultra-wideband (FM-UWB) communication system are provided. The transmitter includes a detector configured to generate a pulse signal when an edge of a digital signal is detected. The transmitter further includes a first modulator configured to modulate the digital signal into a first modulation signal based on a value of the digital signal. The transmitter further includes a second modulator configured to modulate the first modulation signal into a second modulation signal based on a frequency of the first modulation signal when the pulse signal is generated.

Abstract: A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.

Abstract: A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal.

Abstract: Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (??) modulator to operate at a low frequency without generating false lock and glitch noise.

Abstract: A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal.

Abstract: A delay locked loop and method and electronic device including the delay locked loop are provided. In one embodiment, the delay locked loop includes a first delay locked loop and a second delay locked loop. The first delay locked loop receives a data signal and a plurality of first clock signals, generates a plurality of second clock signals based on interpolation on the plurality of first clock signals, selects and outputs one of the second clock signals from among the plurality of second clock signals based on a locking operation on the plurality of second clock signals and the data signal, and generates a plurality of phase resolution control signals.

Abstract: An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.

Abstract: An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.

Abstract: Example embodiments are directed to a delay locked loop (DLL) circuit based on a hybrid finite impulse response (FIR) filtering technique, and a semiconductor memory device including the DLL circuit. The DLL circuit includes a frequency divider and a self-referenced multiphase generator (SRMG) and allows a Sigma-Delta (??) modulator to operate at a low frequency without generating false lock and glitch noise.

Abstract: A delay locked loop and method and electronic device including the delay locked loop are provided. In one embodiment, the delay locked loop includes a first delay locked loop and a second delay locked loop. The first delay locked loop receives a data signal and a plurality of first clock signals, generates a plurality of second clock signals based on interpolation on the plurality of first clock signals, selects and outputs one of the second clock signals from among the plurality of second clock signals based on a locking operation on the plurality of second clock signals and the data signal, and generates a plurality of phase resolution control signals.

Abstract: A frequency divider includes a prescaler and multiple modulus dividers commonly coupled to the prescaler. The prescaler generates intermediate frequency signals having a same phase difference with respect to one another in response to an oscillation frequency signal. The prescaler operates at a first frequency. The modulus dividers respectively divide the intermediate frequency signals with respective ratio to provide a plurality of division frequency signals in response to a control signal. The modulus dividers operate at a second frequency less than the first frequency.

Abstract: An apparatus includes a phase-locked loop (PLL) circuit including a phase-frequency detector configured to output phase error signals. A phase error monitor circuit is configured to determine instantaneous peak phase error by logically combining the phase error signals and comparing pulse widths of the logically combined phase error signals to a programmable delay time at each reference clock cycle to determine instantaneous phase error change. A storage element is configured to store the instantaneous phase error change.