Abstract: A nonvolatile memory device includes a semiconductor substrate including a cell region and a peripheral circuit region, a cell gate on the cell region, and a peripheral circuit gate on the peripheral circuit region, wherein the cell gate includes a charge storage insulating layer on the semiconductor substrate, a gate electrode on the charge storage insulating layer, and a conductive layer on the gate electrode, and the peripheral circuit gate includes a gate insulating layer on the semiconductor substrate, a semiconductor layer on the gate insulating layer, an ohmic layer on the semiconductor layer, and the conductive layer on the ohmic layer.

Abstract: One embodiment of a method for forming a semiconductor device can include forming a gate pattern on a semiconductor substrate and performing a selective re-oxidation process on the gate pattern in gas ambient including hydrogen, oxygen, and nitrogen. When the gate pattern includes a tunnel insulation layer, a metal nitride layer and a metal layer, the selective re-oxidation process heals the etching damage of a gate pattern and simultaneously prevents oxidation of the metal nitride layer and a tungsten electrode.

Abstract: A flash memory device includes a semiconductor substrate, a gate insulating layer having a first width formed on the semiconductor substrate to trap carriers tunneled from the semiconductor substrate and a metal electrode on the gate insulating layer to receive a voltage required for tunneling. The metal electrode having a second width smaller than the first width. The flash memory device further includes a sidewall spacer surrounding a side surface of the metal electrode to prevent oxidation of the metal electrode.

Abstract: Disclosed are a variety of methods for increasing the relative thickness in the peripheral or edge regions of gate dielectric patterns to suppress leakage through these regions. The methods provide alternatives to conventional GPOX processes and provide the improved leakage resistance without incurring the degree of increased gate electrode resistance associated with GPOX processes. Each of the methods includes forming a first opening to expose an active area region, forming an oxidation control region on the exposed portion and then forming a second opening whereby a peripheral region free of the oxidation control region is exposed for formation of a gate dielectric layer. The resulting gate dielectric layers are characterized by a thinner central region surrounded or bounded by a thicker peripheral region.

Abstract: A method of forming a cobalt disilicide layer and a method of manufacturing a semiconductor device using the same are provided. The method of forming a cobalt disilicide layer includes forming a cobalt layer on at least a silicon surface of a semiconductor device using metal organic chemical vapor deposition by supplying a cobalt precursor having a formula Co2(CO)6(R1—C?C—R2), where R1 is H or CH3, and R2 is hydrogen, t-butyl, phenyl, methyl, or ethyl, as a source gas. Then, a capping layer is formed on the cobalt layer. A first thermal treatment is then performed on the semiconductor device in an ultra high vacuum, for example, under a pressure of 10?9-10?3 torr, to react silicon with cobalt. Cobalt unreacted during the first thermal treatment and the capping layer are then removed and a second thermal treatment is performed on the semiconductor device to form the cobalt disilicide (CoSi2) layer.

Abstract: A semiconductor device is fabricated by forming a gate electrode structure, comprising a gate oxide layer pattern, a polysilicon layer pattern, and sidewall spacers on a silicon substrate, forming source/drain regions on both sides of the gate electrode structure in the silicon substrate, depositing a physical vapor deposition (PVD) cobalt layer on the gate electrode structure using PVD, depositing a chemical vapor deposition (CVD) cobalt layer on the PVD cobalt layer using CVD, annealing the silicon substrate to react the PVD and CVD cobalt layers with polysilicon on an upper surface of the gate electrode structure, stripping at least a portion of the PVD cobalt layer and the CVD cobalt layer that has not reacted, and annealing the silicon substrate after stripping the at least the portion of the PVD cobalt layer and the CVD cobalt layer.

Abstract: A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconductor device is annealed to react the double metal layer with the silicon surface. At least a portion of the double layer that has not reacted with the silicon surface is stripped. The semiconductor device is annealed after stripping at least the portion of the double metal layer.

Abstract: Embodiments of the invention provide a method for removing hydrogen gas from a chamber and a method for performing a semiconductor device fabrication sub-process and removing hydrogen gas from a chamber. The method for removing hydrogen gas from a chamber comprises removing a substrate from a chamber, wherein residual hydrogen gas is disposed in the chamber, injecting oxygen gas or ozone gas into the chamber, producing plasma in the chamber, and removing OH radicals from the chamber.

Abstract: A method of forming a silicide film can include forming a first metal film on a silicon substrate and forming a second metal film on the first metal film at a temperature sufficient to react a first portion of the first metal film in contact with the silicon substrate to form a metal-silicide film. The second metal film and a second portion of the first metal film can be removed so that a thin metal-silicide film remains on the silicon substrate. Then, a metal wiring film can be formed on the thin metal-silicide film and the metal wiring film can be etched.

Abstract: The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C?C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.

Abstract: Example embodiments relate to a multilayer gate electrode, a semiconductor device having the same and methods of fabricating the same. Other example embodiments relate to a semiconductor device with a multilayer gate electrode which is relatively stable at higher temperatures, has improved resistance characteristics and improved reliability, and methods of fabricating the same. The multilayer gate electrode may include a polycrystalline semiconductor layer on the gate insulating layer and doped with conductive type impurities, an ohmic contact layer on the polycrystalline semiconductor layer and including tungsten (W1?x) and non-tungsten metal (Mx, x=about 0.01 to about 0.55), a metal barrier layer on the ohmic contact layer and a refractory metal layer on the metal barrier layer.

Abstract: The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C?C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.

Abstract: Example embodiments of the present invention provide a semiconductor device, a gate electrode and method of manufacturing the same. Other example embodiments of the present invention provide a gate electrode with a refractory metal layer having decreased sheet resistance and increased reliability, a semiconductor device and a method of manufacturing the same. The gate electrode may be formed of a polysilicon layer, an amorphized metal barrier layer formed on the polysilicon layer and/or a refractory metal layer formed on the amorphized metal barrier layer. The polysilicon layer may have a first conductivity type. The semiconductor device may include a semiconductor substrate, a source region, a drain region, a gate insulation layer and/or the gate electrode described above. The source region and the drain region may be formed in the semiconductor substrate. The source and drain regions may have the first conductivity type.

Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

Abstract: In a method of manufacturing a semiconductor device including a polysilicon layer on which a heat treatment is performed in hydrogen atmosphere, a preliminary polysilicon layer is formed on a semiconductor substrate. Fluorine (F) impurities are implanted onto the preliminary polysilicon layer, so that the preliminary polysilicon layer is formed into a polysilicon layer. A main heat treatment is performed on the polysilicon layer, thereby preventing a void caused by the fluorine (F) in the polysilicon layer. A subsidiary heat treatment is further performed on the polysilicon layer prior to the main heat treatment, thereby activating dopants in the polysilicon layer. Electrical characteristics and performance of a semiconductor device are improved since the void is sufficiently prevented in the polysilicon layer.

Abstract: In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.

Abstract: Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.

Abstract: A gate structure includes a gate insulation layer on a substrate, a polysilicon layer pattern on the gate insulation layer, a composite metal layer pattern on the polysilicon layer pattern, and a metal silicide layer pattern on a sidewall of the composite metal layer pattern.

Abstract: Methods of forming semiconductor devices are provided. A preliminary gate structure is formed on a semiconductor substrate. The preliminary gate structure includes a gate insulation layer pattern, a polysilicon layer pattern and a conductive layer pattern. A first oxidation process is performed on the preliminary gate structure using an oxygen radical. The first oxidation process is carried out at a first temperature. A second oxidation process is carried out on the oxidized preliminary gate structure to provide a gate structure on the substrate, the second oxidation process being carried out at a second temperature, the second temperature being higher than the first temperature.

Abstract: A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.