Patents by Inventor Woong-Hee Sohn

Woong-Hee Sohn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060051921
    Abstract: In methods of manufacturing semiconductor devices, a preliminary gate oxide layer is formed on a substrate. A surface treatment process is performed on the preliminary gate oxide layer that reduces a diffusion of an oxidizing agent in the preliminary gate oxide layer to form a gate oxide layer on the substrate. A preliminary gate structure is formed on the gate oxide layer. The preliminary gate structure includes a first conductive layer pattern on the gate oxide layer and a second conductive layer pattern on the first conductive layer pattern. An oxidation process is performed on the preliminary gate structure using the oxidizing agent to form an oxide layer on a sidewall of the first conductive layer pattern and on the gate oxide layer, and to round at least one edge portion of the first conductive layer pattern.
    Type: Application
    Filed: August 30, 2005
    Publication date: March 9, 2006
    Inventors: Sun-Pil Youn, Gil-Heyun Choi, Chang-Won Lee, Byung-Hak Lee, Hee-Sook Park, Dong-Chan Lim, Jae-Hwa Park, Woong-Hee Sohn, Jong-Ryeol Yoo
  • Publication number: 20060014355
    Abstract: Embodiments of the present invention include semiconductor devices that can be made with relatively low resistance, and methods of forming the semiconductor devices. A resistance reducing layer is formed between a polysilicon layer and a metal layer. As a result, an interface resistance between the polysilicon layer and the metal layer is greatly reduced and a distribution of the interface resistance is very uniform. As a result, a conductive structure including the resistance reducing layer has a greatly reduced sheet resistance to improve electrical characteristics of a semiconductor device having the conductive structure.
    Type: Application
    Filed: September 23, 2005
    Publication date: January 19, 2006
    Inventors: Jae-Hwa Park, Gil-Heyun Choi, Chang-Won Lee, Byung-Hak Lee, Hee-Sook Park, Woong-Hee Sohn, Jong-Ryeol Yoo, Sun-Pil Yun, Jang-Hee Lee, Dong-Chan Lim
  • Publication number: 20050282338
    Abstract: A method for forming a gate pattern of a semiconductor device can include isotropically etching a gate insulating layer located between a gate conductive layer pattern and a substrate to recess an exposed side wall of the gate insulating layer pattern beyond a lower corner of the gate conductive layer pattern to form an undercut region. The gate conductive layer pattern can be treated to round off the lower corner.
    Type: Application
    Filed: June 15, 2005
    Publication date: December 22, 2005
    Inventors: Jong-Ryeol Yoo, Gil-Heyun Choi, Chang-Won Lee, Byung-Hak Lee, Hee-Sook Park, Dong-Chan Lim, Sun-Pil Youn, Woong-Hee Sohn
  • Publication number: 20050272233
    Abstract: A gate electrode of a transistor can include an interface between a polysilicon conformal layer and a tungsten layer thereon in a trench in a substrate and a capping layer extending across the trench and covering the interface. Related methods are also disclosed.
    Type: Application
    Filed: June 3, 2005
    Publication date: December 8, 2005
    Inventors: Byung-Hak Lee, Chang-Won Lee, Hee-Sook Park, Woong-Hee Sohn, Sun-Pil Youn, Jong-ryeol Yoo
  • Publication number: 20050196945
    Abstract: A metal salicide layer is formed by sequentially depositing a physical vapor deposition (PVD) metal layer and a chemical vapor deposition (CVD) metal layer on a semiconductor device having an exposed silicon surface so as to form a double metal layer. The semiconductor device is annealed to react the double metal layer with the silicon surface. At least a portion of the double layer that has not reacted with the silicon surface is stripped. The semiconductor device is annealed after stripping at least the portion of the double metal layer.
    Type: Application
    Filed: January 27, 2005
    Publication date: September 8, 2005
    Inventors: Jong-ho Yun, Gil-heyun Choi, Seong-hwee Cheong, Sug-woo Jung, Hyun-su Kim, Woong-hee Sohn
  • Publication number: 20050136659
    Abstract: A method of forming a cobalt disilicide layer and a method of manufacturing a semiconductor device using the same are provided. The method of forming a cobalt disilicide layer includes forming a cobalt layer on at least a silicon surface of a semiconductor device using metal organic chemical vapor deposition by supplying a cobalt precursor having a formula Co2(CO)6(R1—C?C—R2), where R1 is H or CH3, and R2 is hydrogen, t-butyl, phenyl, methyl, or ethyl, as a source gas. Then, a capping layer is formed on the cobalt layer. A first thermal treatment is then performed on the semiconductor device in an ultra high vacuum, for example, under a pressure of 10?9-10?3 torr, to react silicon with cobalt. Cobalt unreacted during the first thermal treatment and the capping layer are then removed and a second thermal treatment is performed on the semiconductor device to form the cobalt disilicide (CoSi2) layer.
    Type: Application
    Filed: September 9, 2004
    Publication date: June 23, 2005
    Inventors: Jong-ho Yun, Gil-heyun Choi, Sang-bom Kang, Woong-hee Sohn, Hyun-su Kim
  • Publication number: 20050106859
    Abstract: A method of forming a silicide film can include forming a first metal film on a silicon substrate and forming a second metal film on the first metal film at a temperature sufficient to react a first portion of the first metal film in contact with the silicon substrate to form a metal-silicide film. The second metal film and a second portion of the first metal film can be removed so that a thin metal-silicide film remains on the silicon substrate. Then, a metal wiring film can be formed on the thin metal-silicide film and the metal wiring film can be etched.
    Type: Application
    Filed: October 27, 2004
    Publication date: May 19, 2005
    Inventors: Hyun-su Kim, Gil-heyun Choi, Jong-ho Yun, Sug-woo Jung, Eun-ji Jung, Sang-bom Kang, Woong-hee Sohn
  • Publication number: 20050064706
    Abstract: The present invention provides methods for forming cobalt silicide layers, including introducing a vaporized cobalt precursor onto a silicon substrate to form a cobalt layer. The vaporized cobalt precursor has the formula Co2(CO)6(R1—C?C—R2), wherein R1 is H or CH3, and R2 is H, t-butyl, methyl or ethyl. The silicon substrate is thermally treated so that silicon is reacted with cobalt to form a cobalt silicide layer. Methods for manufacturing semiconductor devices including the cobalt silicide layers described herein and such devices are also provided.
    Type: Application
    Filed: August 23, 2004
    Publication date: March 24, 2005
    Inventors: Hyun-Su Kim, Gil-Heyun Choi, Sang-Bom Kang, Woong-Hee Sohn, Jong-Ho Yun, Kwang-Jin Moon