Patents by Inventor Woytek Tworzydlo
Woytek Tworzydlo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11393901Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.Type: GrantFiled: September 1, 2020Date of Patent: July 19, 2022Assignee: PAKAL TECHNOLOGIES, INCInventors: Richard A. Blanchard, Hidenori Akiyama, Vladimir Rodov, Woytek Tworzydlo
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Patent number: 11145717Abstract: A high power vertical insulated-gate switch is described that includes a parallel cell array having inner cells and an edge cell. The cells have a vertical npnp structure with a trenched field effect device that turns the device on and off. The edge cell is prone to breaking down at high currents. Techniques used to cause the current in the edge cell to be lower than the current in the inner cells, to improve robustness, include: forming a top n-type source region to not extend completely across opposing trenches in areas of the edge cell; forming the edge cell to have a threshold voltage of its field effect device that is greater than the threshold voltage of the field effect devices in the inner cells; and providing a resistive layer between the edge cell and a top cathode electrode electrically contacting the inner cells and the edge cell.Type: GrantFiled: September 30, 2019Date of Patent: October 12, 2021Assignee: Pakal Technologies, Inc.Inventors: Richard A. Blanchard, Vladimir Rodov, Woytek Tworzydlo, Hidenori Akiyama
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Patent number: 11114552Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? drift layer, a p-well, trenched insulated gates formed in the p-well, and n+ regions between at least some of the gates, so that vertical npn and pnp transistors are formed. A cathode electrode is on top, and an anode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the cathode electrode. To direct high energy electrons away from a gate oxide layer on the sidewalls of the trenches, boron is implanted between the trenches so p+ regions are formed in the mesas of the less-doped p-well. The p+ regions break down during an over-voltage event before the p-well breaks down in the mesas.Type: GrantFiled: March 18, 2020Date of Patent: September 7, 2021Assignee: Pakal Technologies, Inc.Inventors: Paul M. Moore, Woytek Tworzydlo, Richard A. Blanchard
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Publication number: 20210028279Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.Type: ApplicationFiled: September 1, 2020Publication date: January 28, 2021Inventors: Richard A. Blanchard, Hidenori Akiyama, Vladimir Rodov, Woytek Tworzydlo
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Patent number: 10797131Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.Type: GrantFiled: March 28, 2019Date of Patent: October 6, 2020Assignee: Pakal Technologies, Inc.Inventors: Richard A. Blanchard, Hidenori Akiyama, Vladimir Rodov, Woytek Tworzydlo
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Publication number: 20200312988Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? drift layer, a p-well, trenched insulated gates formed in the p-well, and n+ regions between at least some of the gates, so that vertical npn and pnp transistors are formed. A cathode electrode is on top, and an anode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the cathode electrode. To direct high energy electrons away from a gate oxide layer on the sidewalls of the trenches, boron is implanted between the trenches so p+ regions are formed in the mesas of the less-doped p-well. The p+ regions break down during an over-voltage event before the p-well breaks down in the mesas.Type: ApplicationFiled: March 18, 2020Publication date: October 1, 2020Inventors: Paul M. Moore, Woytek Tworzydlo, Richard A. Blanchard
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Publication number: 20200105873Abstract: A high power vertical insulated-gate switch is described that includes a parallel cell array having inner cells and an edge cell. The cells have a vertical npnp structure with a trenched field effect device that turns the device on and off. The edge cell is prone to breaking down at high currents. Techniques used to cause the current in the edge cell to be lower than the current in the inner cells, to improve robustness, include: forming a top n-type source region to not extend completely across opposing trenches in areas of the edge cell; forming the edge cell to have a threshold voltage of its field effect device that is greater than the threshold voltage of the field effect devices in the inner cells; and providing a resistive layer between the edge cell and a top cathode electrode electrically contacting the inner cells and the edge cell.Type: ApplicationFiled: September 30, 2019Publication date: April 2, 2020Inventors: Richard A. Blanchard, Vladimir Rodov, Woytek Tworzydlo, Hidenori Akiyama
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Publication number: 20190312106Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.Type: ApplicationFiled: March 28, 2019Publication date: October 10, 2019Inventors: Richard A. Blanchard, Hidenori Akiyama, Vladimir Rodov, Woytek Tworzydlo
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Publication number: 20190115423Abstract: A high power vertical insulated-gate switch is described that includes an active region, containing a cell array, and a surrounding termination region. The termination region is for at least the purpose of controlling a breakdown voltage and does not contain any switching cells. Assuming the anode is the silicon substrate (p-type), it is desirable to have good hole injection efficiency from the substrate in the active region in the device's on-state. Therefore, the substrate should be highly doped (p++) in the active region. It is desirable to have poor hole injection efficiency in the termination region so that there is a minimum concentration of holes in the termination region when the switch is turned off. Various doping techniques are disclosed that cause the substrate to efficiency inject holes into the active region but inefficiently inject holes into the termination region during the on-state.Type: ApplicationFiled: December 5, 2018Publication date: April 18, 2019Inventors: Richard A. Blanchard, Hidenori Akiyama, Vladimir Rodov, Woytek Tworzydlo
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Patent number: 10256331Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N? epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.Type: GrantFiled: March 2, 2018Date of Patent: April 9, 2019Assignee: Pakal Technologies, Inc.Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo, Vladimir Rodov
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Patent number: 10224404Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. To speed up the removal of residual electrons in the p-well after the gate electrode voltage is removed, a p+ region is added adjacent the n+ regions, and an n-layer is added below the p+ region. The cathode electrode directly contacts the p+ region and the n+ regions. During turn-off, the p+ region provides holes which recombine with the residual electrons to rapidly terminate the current flow.Type: GrantFiled: June 23, 2017Date of Patent: March 5, 2019Assignee: Pakal Technologies, Inc.Inventors: Hidenori Akiyama, Vladimir Rodov, Richard A. Blanchard, Woytek Tworzydlo
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Patent number: 10181509Abstract: A high power vertical insulated-gate switch is described that includes an active region, containing a cell array, and a surrounding termination region. The termination region is for at least the purpose of controlling a breakdown voltage and does not contain any switching cells. Assuming the anode is the silicon substrate (p-type), it is desirable to have good hole injection efficiency from the substrate in the active region in the device's on-state. Therefore, the substrate should be highly doped (p++) in the active region. It is desirable to have poor hole injection efficiency in the termination region so that there is a minimum concentration of holes in the termination region when the switch is turned off. Various doping techniques are disclosed that cause the substrate to efficiency inject holes into the active region but inefficiently inject holes into the termination region during the on-state.Type: GrantFiled: August 4, 2016Date of Patent: January 15, 2019Assignee: PAKAL TECHNOLOGIES, LLCInventors: Richard A. Blanchard, Hidenori Akiyama, Vladimir Rodov, Woytek Tworzydlo
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Publication number: 20180254336Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a P+ layer (e.g., a substrate), an N? epi layer, a P-well, vertical insulated gates formed in the P-well, and N+ regions between at least some of the gates, so that vertical NPN and PNP transistors are formed. A source/emitter electrode is on top, and a drain/cathode electrode is on the bottom of the substrate. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gates, referenced to the source/emitter electrode. Some of the cells are passive, having gates that are either not connected to the active gates or having gates that are shorted to their associated N+ regions, to customize the input capacitance and lower the saturation current. Other techniques are described to form the passive cells.Type: ApplicationFiled: March 2, 2018Publication date: September 6, 2018Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo, Vladimir Rodov
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Patent number: 9935188Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the npn transistor to its emitter, to turn the npn transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. The p-channel MOSFET includes a Schottky source formed in the top surface of the npn transistor emitter.Type: GrantFiled: July 20, 2017Date of Patent: April 3, 2018Assignee: Pakal Technologies LLCInventors: Richard A. Blanchard, Vladimir Rodov, Hidenori Akiyama, Woytek Tworzydlo
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Publication number: 20180026121Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the npn transistor to its emitter, to turn the npn transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. The p-channel MOSFET includes a Schottky source formed in the top surface of the npn transistor emitter.Type: ApplicationFiled: July 20, 2017Publication date: January 25, 2018Inventors: Richard A. Blanchard, Vladimir Rodov, Hidenori Akiyama, Woytek Tworzydlo
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Publication number: 20180006120Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate electrodes formed in the p-well, and n+ regions between the gate electrodes, so that vertical npn and pnp transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate electrodes, referenced to the cathode. To speed up the removal of residual electrons in the p-well after the gate electrode voltage is removed, a p+ region is added adjacent the n+ regions, and an n-layer is added below the p+ region. The cathode electrode directly contacts the p+ region and the n+ regions. During turn-off, the p+ region provides holes which recombine with the residual electrons to rapidly terminate the current flow.Type: ApplicationFiled: June 23, 2017Publication date: January 4, 2018Inventors: Hidenori Akiyama, Vladimir Rodov, Richard A. Blanchard, Woytek Tworzydlo
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Patent number: 9806181Abstract: An insulated gate turn-off (IGTO) device has a PNPN layered structure so that vertical NPN and PNP transistors are formed. Trench gates are formed extending into the intermediate P-layer. The device is formed of an array of cells. A P-channel MOSFET, having a trenched gate, is formed in some of the cells. The control terminal of the IGTO device is connected to the insulated gates of all cells, including to the gate of the P-channel MOSFET, and to the intermediate P-layer. To turn the device on, a positive voltage is applied to the control terminal to turn on the NPN transistor by forward biasing its base-emitter. To turn off the IGTO device, a negative voltage is applied to the control terminal to turn on the P-channel MOSFET to short the NPN base to its emitter.Type: GrantFiled: January 12, 2016Date of Patent: October 31, 2017Assignee: Pakal Technologies LLCInventors: Vladimir Rodov, Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo
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Publication number: 20170047395Abstract: A high power vertical insulated-gate switch is described that includes an active region, containing a cell array, and a surrounding termination region. The termination region is for at least the purpose of controlling a breakdown voltage and does not contain any switching cells. Assuming the anode is the silicon substrate (p-type), it is desirable to have good hole injection efficiency from the substrate in the active region in the device's on-state. Therefore, the substrate should be highly doped (p++) in the active region. It is desirable to have poor hole injection efficiency in the termination region so that there is a minimum concentration of holes in the termination region when the switch is turned off. Various doping techniques are disclosed that cause the substrate to efficiency inject holes into the active region but inefficiently inject holes into the termination region during the on-state.Type: ApplicationFiled: August 4, 2016Publication date: February 16, 2017Inventors: Richard A. Blanchard, Hidenori Akiyama, Vladimir Rodov, Woytek Tworzydlo
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Publication number: 20160204239Abstract: An insulated gate turn-off (IGTO) device has a PNPN layered structure so that vertical NPN and PNP transistors are formed. Trench gates are formed extending into the intermediate P-layer. The device is formed of an array of cells. A P-channel MOSFET, having a trenched gate, is formed in some of the cells. The control terminal of the IGTO device is connected to the insulated gates of all cells, including to the gate of the P-channel MOSFET, and to the intermediate P-layer. To turn the device on, a positive voltage is applied to the control terminal to turn on the NPN transistor by forward biasing its base-emitter. To turn off the IGTO device, a negative voltage is applied to the control terminal to turn on the P-channel MOSFET to short the NPN base to its emitter.Type: ApplicationFiled: January 12, 2016Publication date: July 14, 2016Inventors: Vladimir Rodov, Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo
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Patent number: RE47072Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the NPN transistor to its emitter, to turn the NPN transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. This allows the IGTO device to be more easily turned off while in a latch-up condition, when the device is acting like a thyristor.Type: GrantFiled: August 14, 2017Date of Patent: October 2, 2018Assignee: Pakal Technologies, LLCInventors: Vladimir Rodov, Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo