Patents by Inventor Woytek Tworzydlo

Woytek Tworzydlo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9391184
    Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the NPN transistor to its emitter, to turn the NPN transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. This allows the IGTO device to be more easily turned off while in a latch-up condition, when the device is acting like a thyristor.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: July 12, 2016
    Assignee: Pakal Technologies, LLC
    Inventors: Vladimir Rodov, Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo
  • Patent number: 9306048
    Abstract: An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n? layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. Some of the gate regions are first gate regions that only extend into the p-well, and other ones of the gate regions are second gate regions that extend through the p-well and into the n? layer to create a vertical conducting channel when biased. The second gate regions increase the beta of the PNP transistor. When the first gate regions are biased, the base of the NPN transistor is narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The distributed second gate regions lower the minimum gate voltage needed to turn on the thyristor.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: April 5, 2016
    Assignee: Pakal Technologies LLC
    Inventors: Richard A Blanchard, Hidenori Akiyama, Woytek Tworzydlo
  • Publication number: 20150349104
    Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device is formed of a matrix of cells. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for shorting the base of the NPN transistor to its emitter, to turn the NPN transistor off when the p-channel MOSFET is turned on by a slight negative voltage applied to the gate. This allows the IGTO device to be more easily turned off while in a latch-up condition, when the device is acting like a thyristor.
    Type: Application
    Filed: April 30, 2015
    Publication date: December 3, 2015
    Inventors: Vladimir Rodov, Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo
  • Patent number: 8937502
    Abstract: A lateral insulated gate turn-off (IGTO) device includes an n-type layer, a p-well formed in the n-type layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, at least one trenched gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, and an anode electrode electrically contacting the p+ type anode region. The structure forms a lateral structure of NPN and PNP transistors, where the well forms the base of the NPN transistor. When a turn-on voltage is applied to the gate, the p-base has a reduced width, resulting in the beta of the NPN transistor increasing beyond a threshold to turn on the IGTO device by current feedback.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: January 20, 2015
    Assignee: Pakal Technologies LLC
    Inventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo
  • Patent number: 8878237
    Abstract: An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n? epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: November 4, 2014
    Assignee: Pakal Technologies LLC
    Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo
  • Patent number: 8878238
    Abstract: Methods and systems for a gate-controlled thyristor which switches between narrow-base operation in the ON state and wide-base operation in the OFF state, and which can only sustain latch-up in the narrow-base ON state.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: November 4, 2014
    Assignee: Pakal Technologies LLC
    Inventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo
  • Publication number: 20140240027
    Abstract: An insulated gate turn-off (IGTO) device has a layered structure including a p+ layer (e.g., a substrate), an n-type layer, a p-type layer (which may be a p-well), n+ regions formed in the surface of the p-type layer, and insulated planar gates over the p-type layer between the n+ regions. The layered structure forms vertical NPN and PNP transistors. The p-type layer forms the base of the NPN transistor. When the gates are sufficiently positively biased, the underlying p-type layer inverts to reduce the width of the base to increase the beta of the NPN transistor. This causes the product of the betas of the NPN and PNP transistors to exceed one, and the device becomes fully conductive. When the gate voltage is removed, the base width increases such that the product of the betas is less than one, and the device shuts off. No latch-up occurs in normal operation.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 28, 2014
    Applicant: Pakal Technologies, LLC
    Inventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo, Vladimir Rodov
  • Publication number: 20140240025
    Abstract: A lateral insulated gate turn-off (IGTO) device includes an n-type layer, a p-well formed in the n-type layer, a shallow n+ type region formed in the well, a shallow p+ type region formed in the well, a cathode electrode shorting the n+ type region to the p+ type region, at least one trenched gate extending through the n+ type region and into the well, a p+ type anode region laterally spaced from the well, and an anode electrode electrically contacting the p+ type anode region. The structure forms a lateral structure of NPN and PNP transistors, where the well forms the base of the NPN transistor. When a turn-on voltage is applied to the gate, the p-base has a reduced width, resulting in the beta of the NPN transistor increasing beyond a threshold to turn on the IGTO device by current feedback.
    Type: Application
    Filed: February 27, 2014
    Publication date: August 28, 2014
    Applicant: PAKAL TECHNOLOGIES, LLC
    Inventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo
  • Patent number: 8742456
    Abstract: An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: June 3, 2014
    Assignee: Pakal Technologies LLC
    Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo
  • Publication number: 20140091358
    Abstract: Methods and systems for a gate-controlled thyristor which switches between narrow-base operation in the ON state and wide-base operation in the OFF state, and which can only sustain latch-up in the narrow-base ON state.
    Type: Application
    Filed: October 1, 2012
    Publication date: April 3, 2014
    Applicant: Pakal Technologies LLC
    Inventors: Richard A. Blanchard, Hidenori Akiyama, Woytek Tworzydlo
  • Publication number: 20140091855
    Abstract: An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n? layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. Some of the gate regions are first gate regions that only extend into the p-well, and other ones of the gate regions are second gate regions that extend through the p-well and into the n? layer to create a vertical conducting channel when biased. The second gate regions increase the beta of the PNP transistor. When the first gate regions are biased, the base of the NPN transistor is narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The distributed second gate regions lower the minimum gate voltage needed to turn on the thyristor.
    Type: Application
    Filed: September 24, 2013
    Publication date: April 3, 2014
    Applicant: Pakal Technologies, LLC
    Inventors: Richard A Blanchard, Hidenori Akiyama, Woytek Tworzydlo
  • Publication number: 20140054641
    Abstract: An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode.
    Type: Application
    Filed: October 22, 2013
    Publication date: February 27, 2014
    Applicant: Pakal Technologies, LLC
    Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo
  • Publication number: 20140034995
    Abstract: An insulated gate turn-off thyristor, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? layer, a p-well, vertical insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The thyristor is formed of a matrix of cells. Due to the discontinuity along the edge cells, a relatively large number of holes are injected into the n? epi layer and drift into the edge p-well, normally creating a higher current along the edge and lowering the breakover voltage of the thyristor. To counter this effect, the dopant concentration of the n+ region(s) near the edge is reduced to reduce the NPN transistor beta and current along the edge, thus increasing the breakover voltage. Alternatively, a deep trench may circumscribe the edge cells to provide isolation from the injected holes.
    Type: Application
    Filed: July 29, 2013
    Publication date: February 6, 2014
    Applicant: Pakal Technologies LLC
    Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo
  • Patent number: 8569117
    Abstract: An integrated trench-MOS-controlled-thyristor plus trench gated diode combination, in which the trenches are preferably formed at the same time. A backside polarity reversal process permits a backside p+ region in the thyristor areas, and only a backside n+ region in the diode areas (for an n-type device). This is particularly advantageous in motor control circuits and the like, where the antiparallel diode permits the thyristor to be dropped into existing power MOSFET circuit designs. In power conversion circuits, the antiparallel diode can conveniently serve as a freewheeling diode.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 29, 2013
    Assignee: Pakal Technologies LLC
    Inventors: Hidenori Akiyama, Richard A. Blanchard, Woytek Tworzydlo
  • Patent number: 7009253
    Abstract: A method and apparatus for preventing thermo-mechanical damage to an electrostatic discharge (ESD) protection device is disclosed. The method and apparatus of the invention use materials with superior thermo-mechanical properties, in particular, the Coefficient of Thermal Expansion (CTE), melting temperature, tensile strength and fracture toughness. The thermo-mechanical energy absorber materials are incorporated in, or replace, components of the ESD device that are susceptible to thermo-mechanical stress and cracking due to localized heating and thermal expansion.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: March 7, 2006
    Assignee: ESD Pulse, Inc.
    Inventors: Vladimir Rodov, Wlodzimierz Woytek Tworzydlo
  • Patent number: 6853036
    Abstract: A method and apparatus for preventing thermo-mechanical damage to an electrostatic discharge (ESD) protection device is disclosed. The method and apparatus of the invention focus on preventing ESD protection circuit failure due to elastic waves within the materials of an integrated circuit. The elastic waves are specifically caused by very fast ESD discharge events. Disclosed are ESD protection circuits incorporating materials with superior thermo-mechanical properties, in particular, material damping, melting temperature, material stiffness, elastic modulus, tensile strength and fracture toughness. Also disclosed is the use of thermo-mechanical energy absorber material that is designed to protect ESD devices from failure due to slower ESD events.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: February 8, 2005
    Assignee: ESD Pulse, Inc.
    Inventors: Vladimir Rodov, Wlodzimierz Woytek Tworzydlo
  • Patent number: 5946764
    Abstract: A windshield wiper blade assembly equipped with a combination of tilting secondary yokes (38) and airflow deflectors (44) articulated thereon, to provide smooth operation and wind lift resistance at a broad range of driving speeds. Wiper blade assembly (24) is mounted on a distal end of a wiper arm (22) and is driven in a reciprocating motion across a windshield (20). The wiper blade assembly has a wiping element (46) attached to a supporting structure that includes a main yoke (34), two secondary yokes (38) and possibly tertiary yokes (40). Dual-pivot hinges (42) are introduced between main yoke (34) and secondary yokes (36) of the wiper blade. As wiper blade (24) sweeps across windshield (20), the friction force causes limited tilting or canting of the tilting substructure, which includes secondary yokes (38), tertiary yokes (40) and wiping element (46). The tilting produces desirable chatter-resistant angle of attack and reduces squeak. The tilt angle is generally different for each sweep direction.
    Type: Grant
    Filed: June 5, 1997
    Date of Patent: September 7, 1999
    Inventor: Wlodzimierz Woytek Tworzydlo