Abstract: The present invention provides an energy-storing temperature control material, and belongs to the technical field of temperature control materials. In the energy-storing temperature control material provided in the present invention, the organic synthetic fiber based phase-change material has a three-dimensional dispersion effect, and can form a network constraint for remaining phase-change materials to reinforce mechanical properties of the materials, thereby fixing shapes of the materials and avoiding a liquid-crystal phase separation phenomenon in the phase-change process. The phase-change energy storage agent can absorb and release the heat by means of solid-liquid phase conversion of the material, to achieve the temperature control effect; and the phase-change temperature regulator can regulate a phase-change temperature range of the phase-change material, to make the energy-storing temperature control material suitable for climatic features of northern China.

Abstract: A package comprising a substrate comprising at least one dielectric layer and a plurality of interconnects, a first chiplet coupled to the substrate, a second chiplet coupled to the first chiplet, an encapsulation layer coupled to the substrate, the first chiplet and the second chiplet, a plurality of encapsulation interconnects located in the encapsulation layer, a metallization portion coupled to the encapsulation layer, the second chiplet and the plurality of encapsulation interconnects and a first integrated device coupled to the metallization portion.

Abstract: Techniques are disclosed for implementing cross-zone communication for computing zones executing different coding protocols. A server computer system may receive, via a proxy layer of a first instance of an application executing within a first computing zone according to a first set of coding protocols, a request for a service executed via a second instance of the application in a second computing zone according to a second, different set of coding protocols. The system may alter, via a remote layer of the first instance, a set of data specified in the request to comply with the second, set of protocols. The system may transmit, via the remote layer of the first instance to a remote layer of the second instance, the altered set of data. The system may advantageously provide a simplified development interface allowing for both development and testing within a local environment without deployment of multiple different services.

Abstract: Methods, systems, and computer-readable storage media for providing two or more map paths, each map path representing a set of models and relationships between models for data stored in a database system, combining the two or more map paths to provide a map path tree that at least partially defines a data structure for storing at least a portion of the data stored in the database system in the cache, querying the database system by recursively traversing the map path tree to retrieve data instances from the database system, and storing each data instance in the cache using the data structure.

Abstract: The present disclosure is related to a self-starting synchronous reluctance motor rotor, a motor and a compressor. The self-starting synchronous reluctance motor rotor includes a rotor core; the rotor core is provided with a plurality of slit grooves; both ends of each of the slit grooves are respectively provided with a filled groove; a first end of the filled groove is provided adjacent to each slit groove, and a second end of the filled groove extends outwards parallel to the d-axis of the rotor core; the second end of the filled groove is provided with at least one bevel edge, so that when the d-axis magnetic flux of the rotor core enters a stator along channels formed at the bevel edges, no abrupt change occurs to the magnetic flux.

Abstract: Vertical channel field-effect transistors (VCFETs) with reduced contact resistance and/or parasitic capacitance, and related fabrication methods. In exemplary aspects, to reduce contact resistance of the VCFET, an end portion of the vertical channel has a semiconductor structure that has an expanded width in the horizontal direction parallel to the substrate surface. This provides a greater area to form a contact for a source/drain to reduce contact resistance of the VCFET. To reduce the parasitic capacitance between the gate and a contact of the VCFET, the spacer includes one or more air gaps that form an air spacer(s) between the gate and the contact to reduce the overall average permittivity of the spacer. In one example, the air spacer(s) of the VCFET is elongated in the horizontal direction parallel to the substrate surface (and perpendicular to the vertical direction of the vertical channel) to further reduce the parasitic capacitance.

Abstract: A method for operating a graph database, including receiving, by a computer system, a query to a particular graph database, the query identifying a plurality of vertices of the particular graph database. The method further includes performing, by the computer system, hash operations on two or more of the plurality of vertices to generate respective hash values and dividing, using the respective hash values, the query into a plurality of sub-queries, each corresponding to a subset of the plurality of vertices. The method also includes sending, by the computer system, ones of the plurality of sub-queries to a plurality of database repositories for the particular graph database.

Abstract: The invention discloses a biological desulfurizer for removing organic sulfur in fracturing flowback fluid and application thereof. The biological desulfurizer includes a compound with a triazine structure formed by modifying chitosan with aldehydes and inorganic salts. The triazine structure has a good removal effect on hydrogen sulfide and organic sulfur such as mercaptan and sulfide. The biological desulfurizer of the invention has a sulfur capacity of up to 250 g/kg and a desulfurization efficiency of over 95% in 15 min. It can effectively remove the stink of sulfur-containing working water, improve the working environment of the well site, and reduce the impact of sulfur compounds on the atmospheric environment during the development of oil and gas fields.

Abstract: A display may be formed by an array of light-emitting diodes mounted to the surface of a display substrate. The light-emitting diodes may be inorganic light-emitting diodes formed from separate crystalline semiconductor structures. An array of pixel control circuits may be used to control light emission from the light-emitting diodes. Each pixel control circuit may be configured to control one or more respective passive matrices. To control partial pixel cells in the display, a donor pixel control circuit in a partial pixel cell may control the pixels in a receptor partial pixel cell without a pixel control circuit. To mitigate the size of an inactive area of the display, fanout signal lines for the display may be formed in the light-emitting active area of the display. The fanout signal lines may be formed between a row of pixel control circuits and a bottom edge of the light-emitting active area.

Abstract: In response to receiving a request for an identity key from a first entity, an identity key for the first entity is generated. A first request from the first entity to replicate a set of data is received. The generated identity key for the first entity is added to the metadata of the set of data requested to be replicated. A determination is made whether a replication rule exists for the first entity. In response to determining that a replication rule exists for the first entity, the set of data is replicated according to the replication rule for the first entity.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. These systems and methods can use a neural network based predictor, that has been trained to determine a temperature rise across an entire IC. The training of the predictor can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC), each template associated with location parameters to position the template in the IC; performing thermal simulations for each respective template of the IC, each thermal simulation determining an output based on a power pattern of tiles of the respective template, the output indicating a change in temperature of a center tile of the respective template relative to a base temperature of the integrated circuit; and training a neural network.

Abstract: The present disclosure provides a resource utilization method of crude sodium sulfate. The method comprises the following step: reducing the crude sodium sulfate to form a sodium sulfide solution; making the sodium sulfide solution perform a first reaction with chlorine to obtain sulfur and a sodium chloride solution; and electrolyzing the sodium chloride solution to obtain a sodium hydroxide solution and chlorine, and supplying the generated chlorine to the sodium sulfide solution to perform the first reaction.

Abstract: Provided are a boron-silicon heterocyclic compound having a structure represented by formula 1, a display device and a display apparatus. In formula 1, L1 and L2 are each a single bond, C6-C30 arylene, C6-C30 fused arylene, C4-C30 heteroarylene, or C4-C30 fused heteroarylene; D1 and D2 are each a substituted or unsubstituted C6-C60 aryl, a substituted or unsubstituted C4-C60 heteroaryl, a substituted or unsubstituted C10-C60 fused aryl, a substituted or unsubstituted C8-C30 fused heteroaryl, or a substituted or unsubstituted diphenylamino. The compound has a strong inductive effect and can reduce the driving voltage of the device. The silacyclopentadiene having a silicon atom as spiro-atom can effectively improve the solubility of the material, which is beneficial to the cleaning of the vapor deposition mask. In addition, the compound has a higher triplet energy level to effectively transfer energy to the luminous body, and improves the efficiency of the device.

Abstract: Machine assisted systems and methods for enhancing the resolution of an IC thermal profile from a system analysis are described. The methods can include generating a representation of two or more templates identifying different portions of an integrated circuit (IC); performing a thermal simulation for each respective template of the IC based on a sequence of power patterns of tiles of the respective template; and training a neural network with a plurality of training data collected via thermal simulations performed for the templates of the IC. These systems and methods can use a machine learning predictor, that has been trained to determine a transient temperature rise across an entire IC, and then append the determined transient temperature rise to a system level thermal profile of the IC.

Abstract: Disclosed is a complementary field effect transistor (CFET) formed from stacked 2D-material transistors. The 2D-material transistors are formed from transition metal dichalcogenide (TMD), which are atomically thin semiconductors. The stacked TMD transistors allow for enhanced drive current and lower switching capacitance, both of which are desirable.

Abstract: A device may receive input data associated with a wireless network, and may extract data from the input data to generate extracted data. The device may create PRB images based on the extracted data, and may process the PRB images, with a first model, to associate labels with each of the PRB images. The device may process the labels and the PRB images, with a second model, to identify potential issues associated with the PRB images, and may process data identifying the potential issues associated with the PRB images, with a third model, to compress the data identifying the potential issues into an array. The device may process the array, with a fourth model, to determine probability scores associated with the potential issues, and may select a potential issue with a greatest probability score as a detected issue. The device may perform actions based on the detected issue.

Abstract: A monolithic 3D complementary field-effect transistor (FET) (CFET) circuit includes a first CFET structure and a second CFET structure in a logic circuit within a device layer. A first interconnect layer disposed on the device layer provides first and second input contacts and an output contact of a logic circuit. Each CFET structure includes an upper FET having a first type (e.g., P-type or N-type) on a lower FET having a second type (e.g., N-type or P-type). The FETs in the monolithic 3D CFET circuit may be interconnected to form a two-input NOR circuit or a two-input NAND circuit. Vertical access interconnects (vias) may be formed within the device layer to interconnect the FETs externally and to each other. The FETs may be formed as bulk-type transistors or SOI transistors.

Abstract: The present application provides a rotor assembly and a self-starting permanent magnet synchronous reluctance motor. The rotor assembly includes a rotor core, wherein on a cross section of the rotor core, the rotor core is provided with slit slots, q-axis squirrel cage slots and permanent magnets, the q-axis squirrel cage slots are disposed at two ends of the slit slots, the permanent magnets are disposed in the slit slots, the permanent magnet located at the innermost layer in a d-axis direction is at least asymmetrically disposed relative to a d-axis, and an offset direction of the permanent magnet located at the innermost layer relative to the d axis is consistent with a rotation direction of the rotor assembly.

Abstract: A system includes a first park circuit having a signal input, an output, and a control input. The system also includes a first signal path having an input and an output, wherein the input of the first signal path is coupled to the output of the first park circuit. The system also includes a second park circuit having a signal input, an output, and a control input, wherein the signal input of the second park circuit is coupled to the output of the first signal path. The system further includes a second signal path having an input and an output, wherein the input of the second signal path is coupled to the output of the second park circuit.

Abstract: A stacked gate-all-around (GAA) complementary field-effect transistor (CFET) includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA ITT includes at least one three-dimensional (3D) semiconductor slab with a channel region and a first surface. A first gate structure surrounds the channel region in the first GAA FET, and a second gate structure surrounds the channel region in the second GAA FET. The first gate structure is stacked opposite the second gate structure in a direction orthogonal to the first surface. In some examples, a first crystal structure of the 3D semiconductor slab in the first GAA FET has a first orientation, and a second crystal structure of the 3D semiconductor slab in the second GAA FET has a different orientation for improved carrier mobility.