Abstract: A single-phase permanent magnet synchronous motor and dust collector. The single-phase permanent magnet synchronous motor includes a plurality of stator teeth, the plurality of stator teeth include at least: a first-type and second-type stator tooth; the first-type and second-type stator teeth enclose an annular working cavity for accommodating a rotor part, where the size of a central angle corresponding to a first contour line of an end face of the first-type stator tooth facing the rotor part is different from the size of a central angle corresponding to a second contour line of an end face of the second-type stator tooth facing the rotor part The motor has a significantly reduced cogging torque, a greatly reduced torque ripple, and an obviously increased motor output torque. The single-phase permanent magnet synchronous motor is small in size, light in weight, simple in structure, convenient for large-scale manufacture and low in manufacturing cost.

Abstract: A local active matrix display panel, circuits and methods of operation are described. In an embodiment, a local active matrix display panel includes an array of pixel driver chip, a thin film transistor layer in electrical contact with the array of pixel driver chips, and an array of light emitting diodes electrically connected with the thin film transistor layer.

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes an in-memory computation array having a plurality of computation circuits, each of the computation circuits being configured to perform a dot product computation. In certain aspects, each of the computation circuits includes a memory cell, a capacitive element, a precharge transistor coupled between an output of the memory cell and the capacitive element, and a read transistor coupled between a read bit line (RBL) and the capacitive element.

Abstract: Disclosed are examples of multiple bit magnetoresistive random access memory (MRAM) cells. A multiple bit MRAM cell may comprise a fixed layer, alternately stacked N tunnel barriers and N free layers, and a tunnel cap. N, which may represent number of bits of the MRAM cell, may be greater than or equal to two. Magnetic moment of the fixed layer may be fixed in one perpendicular direction. Magnetic moments of the free layers may be switchable from one to other perpendicular directions upon application of switch currents. The switch currents may be different for different layers. The magnetic moments of the free layers may be switched separately or otherwise independently of other free layers when the switch currents are applied separately.

Abstract: Systems, devices, methods, and computer readable medium for evaluating visual quality of digital content are disclosed. Methods can include identifying content assets including one or more images that are combined to create different digital components distributed to one or more client devices. A quality of each of the one or more images is evaluated using one or more machine learning models trained to evaluate one or more visual aspects that are deemed indicative of visual quality. An aggregate quality for the content assets is determined based, at least in part, on an output of the one or more machine learning models indicating the visual quality of each of the one or more images. A graphical user interface of a first computing device is updated to present a visual indication of the aggregate quality of the content assets.

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes a first memory cell, and a first computation circuit. The first computation circuit may include a first switch having a control input coupled to an output of the first memory cell, a second switch coupled between a node of the first computation circuit and the first switch, a control input of the second switch being coupled to a discharge word-line (DCWL), a capacitive element coupled between the node and a reference potential node, a third switch coupled between the node and a read bit-line (RBL), and a fourth switch coupled between the node and an activation (ACT) line.

Abstract: The present application discloses a method for determining time information, including: detecting a signal of a periodic block, and recording a timestamp of the periodic block; and determining a time at which a time information message to be sent according to the timestamp of the periodic block matched with the time information message, and generating a timestamp of the time information message. The present application further discloses an apparatus and device for determining time information, and a storage medium.

Abstract: A device may receive input data associated with a wireless network, and may extract data from the input data to generate extracted data. The device may create PRB images based on the extracted data, and may process the PRB images, with a first model, to associate labels with each of the PRB images. The device may process the labels and the PRB images, with a second model, to identify potential issues associated with the PRB images, and may process data identifying the potential issues associated with the PRB images, with a third model, to compress the data identifying the potential issues into an array. The device may process the array, with a fourth model, to determine probability scores associated with the potential issues, and may select a potential issue with a greatest probability score as a detected issue. The device may perform actions based on the detected issue.

Abstract: Certain aspects provide methods and apparatus for multiplication of digital signals. In accordance with certain aspects, a multiplication circuit may be used to multiply a portion of a first digital input signal with a portion of a second digital input signal via a first multiplier circuit to generate a first multiplication signal, and multiply another portion of the first digital input signal with another portion of the second digital input signal via a second multiplier circuit to generate a second multiplication signal. A third multiplier circuit and multiple adder circuits may be used to generate an output of the multiplication circuit based on the first and second multiplication signals.

Abstract: Disclosed is apparatus including a vertical spiral inductor. The vertical spiral inductor may include a plurality of dielectric layers formed on a substrate, a plurality of conductive layers, each of the plurality of conductive layers disposed on each of the plurality of dielectric layers, a plurality of insulating layers, each of the plurality of insulating layers disposed on each of the plurality of conductive layers, wherein each of the plurality of insulating layers separates each of the plurality of dielectric layers. A first spiral coil is arranged in a first plane perpendicular to the substrate, where the first spiral coil is formed of first portions of the plurality of conductive layers and a first set of vias of a plurality of vias, configured to connect the first portions of the plurality of conductive layers.

Abstract: Systems, devices, methods, and computer readable medium for evaluating visual quality of digital content are disclosed. Methods can include training machine learning models on images. A request is received to evaluate quality of an image included in a current version of a digital component generated by the computing device. The machine learning models are deployed on the image to generate a score for each quality characteristic of the image. A weight is assigned to each score to generate weighted scores. The weighted scores are combined to generate a combined score for the image. The combined score is compared to one or more thresholds to generate a quality of the image.

Abstract: The present disclosure relates to a compound, a material for an organic electroluminescent device and an application thereof. The compound has a structure represented by Formula (1). The compound has a relatively high refractive index in the region of visible light (400-750 nm), which is conducive to improving the light-emitting efficiency.

Abstract: Disclosed are examples of a device including a front side metallization portion having a front side BEOL. The device also includes a backside BEOL. The device also includes a substrate, where the substrate is disposed between the backside BEOL and the front side metallization portion. The device also includes a metal-insulator-metal (MIM) capacitor embedded in the backside BEOL.

Abstract: A distributed feedback (DFB) laser that includes a substrate comprising a first surface and a second surface, wherein the substrate comprises silicon; a plurality of shallow trench isolations (STIs) located over the second surface of the substrate; a grating region located over the plurality of STIs and the substrate, wherein the grating region comprises a III-V semiconductor material; a non-intentional doping (NID) region located over the grating region; and a contact region located over the NID region.

Abstract: A chaotic stirring device combining plasma arc smelting and permanent magnet including a furnace body; the furnace body is provided therein with a water-cooled copper crucible; the center of an upper surface of the water-cooled copper crucible is a groove for placing raw metals, and the water-cooled copper crucible is internally a hollow cavity; a return pipe is disposed directly below the groove in the hollow cavity; an upper end of the return pipe is vertical upward, and is horizontally provided with a filter screen; a spherical magnet is placed between the filter screen and the groove; one side of the water-cooled copper crucible is provided with a first water inlet pipe and a first water outlet pipe; the first water inlet pipe is connected to the hollow cavity, and the first water outlet pipe is connected to the bottom of the return pipe.

Abstract: An exemplary high performance P-type field-effect transistor (PFET) fabricated on a silicon (Si) germanium (Ge)(SiGe) buffer layer with a SiGe source and drain having a Ge percentage higher than a threshold that causes dislocations at a Si substrate interface is disclosed. A source and drain including a Ge percentage above a 45% threshold provide increased compressive strain in the channel for higher performance of the PFET. Dislocations are avoided in the lattices of the source and drain by forming the PFET on a SiGe buffer layer rather than directly on a Si substrate and the SiGe buffer layer has a percentage of Ge less than a percentage of Ge in the source and drain. In one example, a lattice of the buffer layer is relaxed by implanting dislocations at an interface of the buffer layer and the Si substrate and annealing the buffer layer.

Abstract: An integrated device that includes a substrate, a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled to only the gate.

Abstract: Certain aspects of the present disclosure generally relate to a semiconductor device with buried rails (e.g., buried power and ground rails). One example semiconductor device generally includes a substrate; a first rail, wherein a portion of the first rail is disposed in the substrate, the portion of the first rail having a first width greater than a second width of another portion of the first rail; a second rail, wherein a portion of the second rail is disposed in the substrate, the portion of the second rail having a third width greater than a fourth width of another portion of the second rail; and one or more transistors disposed above the substrate and between the first rail and the second rail.

Abstract: The present disclosure provides a direct starting synchronous reluctance motor rotor, a motor and a rotor manufacturing method. The direct starting synchronous reluctance motor rotor comprises: a rotor core provided with a plurality of slit grooves, two ends of each of the slit grooves being provided with a filling groove respectively to form a magnetic barrier layer, a first end of the filling groove being disposed adjacent to the slit groove, a second end of the filling groove being extended towards an outside of the rotor core, and an outer peripheral surface of the rotor core being provided with a notch communicated with the second end of the filling groove.

Abstract: The present disclosure provides a direct starting synchronous reluctance motor rotor, and a motor. The direct starting synchronous reluctance motor rotor comprises: a rotor core provided with a plurality of slit grooves, two filling grooves are respectively disposed at two ends of each of the slit grooves to form a magnetic barrier layer, a first end of the filling groove being disposed adjacent to the slit groove, a second end of the filling groove being disposed to be extended outwards an outside of the rotor core, a beveled edge is disposed on the second end of at least one of the filling grooves away from a d-axis of the rotor core, so that a d-axis flux of the rotor core will not suddenly change when entering a stator along a channel formed at the beveled edge.