Patents by Inventor Xian Liu

Xian Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139348
    Abstract: Disclosed are a multi-modality molecular imaging probe, and a preparation method and use thereof. The multi-modality molecular imaging probe has an ABA structure, with a magnetic functional unit of a gadolinium complex at the center, and two identical phosphorescent functional units of an iridium complex, which are reasonably integrated into the same one complex molecule. The multi-modality molecular imaging probe simultaneously introduces two optical functional units of the iridium complex and one magnetic functional unit of a gadolinium chelate in the same one complex molecule, which exhibits magnetic-optical dual functional properties. It therefore could be used to prepare both a contrast agent for magnetic resonance imaging and an optical probe for optical imaging.
    Type: Application
    Filed: September 12, 2023
    Publication date: May 2, 2024
    Inventors: Jiaxi Ru, Xiaoliang Tang, Xiufeng Huang, Weisheng Liu, Chao Liang, Lingling Kang, Xiaofen Chen, Xian Shen
  • Patent number: 11973206
    Abstract: A safety device comprises a first heat dissipation part, a second heat dissipation part and a connecting part. The connecting part is arranged between the first heat dissipation part and the second heat dissipation part, and at least one heat locking hole disposed thereon. The heat locking hole of the connecting part can reduce a diffusion speed of heat of the connecting part, so that the heat is concentrated between the first heat locking hole and the second heat locking hole, and thus the connecting part can be fused in time at a high temperature.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 30, 2024
    Assignee: Globe (Jiangsu) Co., Ltd
    Inventors: Chuanjun Liu, Ming Luo, Huage Wang, Xian Zhuang
  • Patent number: 11967225
    Abstract: The present disclosure provides techniques for implementing a video click via a Bluetooth device. The techniques comprise performing matching with and connection to a wireless device; monitoring a signal sent by the wireless device; parsing the signal and determining whether the signal is associated with a preset power-conserving wireless personal area network service; determining whether a terminal device is in a state of playing a video in response to determining that the signal is associated with the preset power-conserving wireless personal area network service; and in response to determining that the terminal device is in the state of playing the video, rendering an effect on the video played by the terminal device based on the signal and updating data based on the signal.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: April 23, 2024
    Assignee: SHANGHAI BILIBILI TECHNOLOGY CO., LTD.
    Inventors: Cong Liu, Haifeng Wang, Xian Lin
  • Patent number: 11968829
    Abstract: A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: April 23, 2024
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Zhuoqiang Jia, Leo Xing, Xian Liu, Serguei Jourba, Nhan Do
  • Publication number: 20240116771
    Abstract: The present disclosure relates to the technical field of oxygen carrier, discloses a medium-entropy perovskite oxygen carrier and its preparation method and application thereof, the synthesis procedure includes preparing an aqueous solution from metallic nitrate serving as a raw material, performing a coprecipitation reaction with at least one of aqueous ammonia solution, a sodium hydroxide aqueous solution or a sodium carbonate aqueous solution as a precipitant at a pH value of 9.5 to 10.5; obtaining the La3CoMnAlO9 powers after stirring, standing, washing, drying and calcining. The preparation method is simple, synthetic conditions are easy to control, and batch production could be achieved.
    Type: Application
    Filed: May 26, 2023
    Publication date: April 11, 2024
    Inventors: Jinlong Gong, Xianhua Zhang, Chunlei Pei, Zhi-Jian Zhao, Xian Yao, Yifan Liu
  • Patent number: 11943221
    Abstract: Aspects of the invention include systems and methods configured to prevent masquerading service attacks. A non-limiting example computer-implemented method includes sending, from a first server in a cloud environment, a communication request comprising an application programming interface (API) key and a first server identifier to an identity and access management (IAM) server of the cloud environment. The API key can be uniquely assigned by the IAM server to a first component of the first server. The first server receives a credential that includes a token for the first component and sends the credential to a second server. The second server sends the credential, a second server identifier, and an identifier for a second component of the second server to the IAM server. The second server receives an acknowledgment from the IAM server and sends the acknowledgment to the first server.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: March 26, 2024
    Assignee: International Business Machines Corporation
    Inventors: Sen Wang, Mei Liu, Si Bo Niu, Wen Yi Gao, Zong Xiong Z X Wang, Guoxiang Zhang, Xiao Yi Tian, Xian Wei Zhang
  • Publication number: 20240088678
    Abstract: The invention provides a voltage balancing system for balancing controlling of voltage of battery cells including a first set of battery cells and a second set of battery cells connected in series. The system includes a high-side analog front end (AFE) connected to the first set of battery cells, a low-side analog front end (AFE) connected to the second set of battery cells, a microcontroller communicating with the high-side AFE and the low-side AFE, and a communication isolating module interconnecting between the high-side AFE and the microcontroller. The system further includes a balancing module arranged at a back end of the low-side AFE or the high-side AFE to equalize voltages output by the low-side AFE and the high-side AFE. Compared with the prior arts, the system employs a balancing module to balance the voltages of the two sets of battery cells, which can shorten the voltage difference therebetween.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Ming Luo, Chuanjun Liu, Xian Zhuang
  • Patent number: 11799005
    Abstract: A method of forming a memory device that includes forming a first insulation layer, a first conductive layer, and a second insulation layer on a semiconductor substrate, forming a trench in the second insulation layer to expose the upper surface of the first conductive layer, performing an oxidation process and a sloped etch process to reshape the upper surface to a concave shape, forming a third insulation layer on the reshaped upper surface, forming a conductive spacer on the third insulation layer, removing portions of the first conductive layer leaving a floating gate under the conductive spacer with the reshaped upper surface terminating at a side surface at a sharp edge, and forming a word line gate laterally adjacent to and insulated from the floating gate. The conductive spacer includes a lower surface that faces and matches the shape of the reshaped upper surface.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: October 24, 2023
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Leo Xing, Chunming Wang, Xian Liu, Nhan Do, Guo Xiang Song
  • Publication number: 20230333209
    Abstract: This application discloses a gesture recognition method and apparatus accurately recognizes a gesture of a user and improves user experience. The method includes: obtaining echo data of a radar, where the echo data includes information generated when an object moves in a detection range of the radar; filtering out, from the echo data, information that does not meet a preset condition, to obtain gesture data, where the preset condition includes at least two of a distance, a speed, or an angle, the distance includes a distance between the object and the radar, the speed includes a speed of the object relative to the radar, and the angle includes an azimuth or a pitch angle of the object in the detection range of the radar; extracting a feature from the gesture data, to obtain gesture feature information; and obtaining a target gesture based on the gesture feature information.
    Type: Application
    Filed: June 19, 2023
    Publication date: October 19, 2023
    Inventors: Xian LIU, Zhiwei YI, Junjie WU, Tao HU, Han JIANG
  • Publication number: 20230292504
    Abstract: A method includes recessing an upper surface of a substrate in first and second areas relative to a third area, forming a first conductive layer in the first area, forming a second conductive layer in the three areas, selectively removing the first and second conductive layers in the first area, while maintaining the second conductive layer in the second and third areas, leaving pairs of stack structures in the first area respectively having a control gate of the second conductive layer and a floating gate of the first conductive layer, forming a third conductive layer in the three areas, recessing the upper surface of the third conductive layer below tops of the stack structures and removing the third conductive layer from the second and third areas, removing the second conductive layer from the second and third areas, and forming blocks of metal material in the second and third areas.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 14, 2023
    Inventors: Zhuoqiang Jia, Leo Xing, Xian Liu, Serguei Jourba, Nhan Do
  • Publication number: 20230290864
    Abstract: A method of forming a device on a silicon substrate having first, second and third areas includes recessing an upper substrate surface in the first and third areas, forming an upwardly extending silicon fin in the second area, forming first source, drain and channel regions in the first area, forming second source, drain and channel regions in the fin, forming third source, drain and channel regions in the third area, forming a floating gate over a first portion of the first channel region using a first polysilicon deposition, forming an erase gate over the first source region and a device gate over the third channel region using a second polysilicon deposition, and forming a word line gate over a second portion of the first channel region, a control gate over the floating gate, and a logic gate over the second channel region using a metal deposition.
    Type: Application
    Filed: May 25, 2022
    Publication date: September 14, 2023
    Inventors: Serguei Jourba, Catherine Decobert, Feng Zhou, Jinho Kim, Xian Liu, Nhan Do
  • Patent number: 11737266
    Abstract: A method of forming a semiconductor device by recessing the upper surface of a semiconductor substrate in first and second areas but not a third area, forming a first conductive layer in the three areas, forming a second conductive layer in all three areas, removing the first and second conductive layers from the second area and portions thereof from the first area resulting in pairs of stack structures each with a control gate over a floating gate, forming a third conductive layer in all three areas, forming a protective layer in the first and second areas and then removing the third conductive layer from the third area, then forming blocks of dummy conductive material in the third area, then etching in the first and second areas to form select and HV gates, and then replacing the blocks of dummy conductive material with blocks of metal material.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: August 22, 2023
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Guo Xiang Song, Chunming Wang, Leo Xing, Xian Liu, Nhan Do
  • Publication number: 20230262975
    Abstract: A method of forming a device on a semiconductor substrate having first, second, third and dummy areas, includes recessing the substrate upper surface in the first, second and dummy areas, forming a first conductive layer over the substrate, removing the first conductive layer from the third area and a second portion of the dummy area, forming a first insulation layer over the substrate, forming first trenches through the first insulation layer and into the substrate in the third area and the second portion of the dummy area, forming second trenches through the first insulation layer, the first conductive layer and into the substrate in the first and second areas and a first portion of the dummy area, and filling the first and second trenches with insulation material. Then, memory cells are formed in the first area, HV devices in the second area and logic devices in the third area.
    Type: Application
    Filed: May 16, 2022
    Publication date: August 17, 2023
    Inventors: Zhuoqiang Jia, Leo Xing, Xian Liu, Serguei Jourba, Nhan Do
  • Publication number: 20230238453
    Abstract: A simplified method for forming pairs of non-volatile memory cells using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. A pair of spaced apart insulation blocks are formed on the first polysilicon layer. Exposed portions of the first poly silicon layer are removed while maintaining a pair of polysilicon blocks of the first polysilicon layer each disposed under one of the pair of insulation blocks. A second polysilicon layer is formed over the substrate and the pair of insulation blocks in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed between the pair of insulation blocks), a second polysilicon block (disposed adjacent an outer side of one insulation block), and a third polysilicon block (disposed adjacent an outer side of the other insulation block).
    Type: Application
    Filed: March 27, 2023
    Publication date: July 27, 2023
    Inventors: Feng Zhou, XIAN LIU, CHIEN-SHENG SU, Nhan DO, CHUNMING WANG
  • Patent number: 11686950
    Abstract: An atmosphere starry sky light for festival entertainment is provided. The constellation unit is configured to switch patterns of twelve constellations and perform projection display on the patterns of the twelve constellations. The starry sky unit is configured to project a starry sky background. The background unit is configured to project patterns of aurora, clouds, and ripples. The planetary unit is configured to switch patterns of a planet, and to project and display a planetary image. The constellation unit, the planetary unit, the starry sky unit and the background unit form a panoramic image of the cosmic starry sky by superimposing and combining.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: June 27, 2023
    Assignee: ZHONGSHAN BOLANG ELECTRONIC TECHNOLOGY CO., LTD.
    Inventor: Ke Xian Liu
  • Publication number: 20230189520
    Abstract: A method of forming memory cells, high voltage devices and logic devices on fins of a semiconductor substrate's upper surface, and the resulting memory device formed thereby. The memory cells are formed on a pair of the fins, where the floating gate is disposed between the pair of fins, the word line gate wraps around the pair of fins, the control gate is disposed over the floating gate, and the erase gate is disposed over the pair of fins and partially over the floating gate. The high voltage devices include HV gates that wrap around respective fins, and the logic devices include logic gates that are metal and wrap around respective fins.
    Type: Application
    Filed: January 30, 2023
    Publication date: June 15, 2023
    Inventors: Guo Xiang Song, Chunming Wang, Leo Xing, Xian Liu, Nhan Do
  • Patent number: 11652162
    Abstract: A simplified method for forming a non-volatile memory cell using two polysilicon depositions. A first polysilicon layer is formed on and insulated from the semiconductor substrate in a first polysilicon deposition process. An insulation block is formed on the first polysilicon layer. Spacers are formed adjacent first and second sides of the insulation block, and with the spacer adjacent the first side is reduced. Exposed portions of the first poly silicon layer are removed while maintaining a polysilicon block of the first polysilicon layer disposed under the insulation block. A second polysilicon layer is formed over the substrate and the insulation block in a second polysilicon deposition process. Portions of the second polysilicon layer are removed while maintaining a first polysilicon block (disposed adjacent the first side of the insulation block), and a second polysilicon block (disposed adjacent the second side of the insulation block).
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: May 16, 2023
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Feng Zhou, Xian Liu, Chien-Sheng Su, Nhan Do, Chunming Wang
  • Patent number: 11646078
    Abstract: Numerous embodiments of circuitry for a set-while-verify operation and a reset-while verify operation for resistive random access memory cells are disclosed. In one embodiment, a set-while-verify circuit for performing a set operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the set operation is complete. In another embodiment, a reset-while-verify circuit for performing a reset operation on a selected RRAM cell in the array applies a combination of voltages or current to a bit line, word line, and source line associated with the selected RRAM cell and stops said applying when the reset operation is complete.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: May 9, 2023
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Hieu Van Tran, Anh Ly, Thuan Vu, Stanley Hong, Feng Zhou, Xian Liu, Nhan Do
  • Patent number: D990028
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: June 20, 2023
    Assignee: ZHONGSHAN BOLANG ELECTRONIC TECHNOLOGY CO., LTD.
    Inventors: Yong Huang, Ke Xian Liu
  • Patent number: D997435
    Type: Grant
    Filed: December 3, 2021
    Date of Patent: August 29, 2023
    Assignee: ZHONGSHAN BOLANG ELECTRONIC TECHNOLOGY CO., LTD.
    Inventors: Ke Xian Liu, Gang Wang