Patents by Inventor Xiangfeng Duan
Xiangfeng Duan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20090065764Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).Type: ApplicationFiled: November 5, 2008Publication date: March 12, 2009Applicant: NANOSYS, Inc.Inventors: David L. Heald, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
-
Patent number: 7501315Abstract: Methods for forming or patterning nanostructure arrays are provided. The methods involve formation of arrays on coatings comprising nanostructure association groups, patterning using resist, and/or use of devices that facilitate array formation. Related devices for forming nanostructure arrays are also provided, as are devices including nanostructure arrays (e.g., memory devices).Type: GrantFiled: June 7, 2005Date of Patent: March 10, 2009Assignee: Nanosys, Inc.Inventors: David L. Heald, Karen Chu Cruden, Xiangfeng Duan, Chao Liu, J. Wallace Parce
-
Publication number: 20090057650Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.Type: ApplicationFiled: February 27, 2008Publication date: March 5, 2009Applicant: President and Fellows of Harvard CollegeInventors: Charles M. Lieber, Xiangfeng Duan, Yi Cui, Yu Huang, Mark Gudiksen, Lincoln J. Lauhon, Jianfang Wang, Hongkun Park, Qingqiao Wei, Wenjie Liang, David C. Smith, Deli Wang, Zhaohui Zhong
-
Patent number: 7476596Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor.Type: GrantFiled: October 4, 2006Date of Patent: January 13, 2009Assignee: President and Fellows of Harvard CollegeInventors: Charles M. Lieber, Yi Cui, Xiangfeng Duan, Yu Huang
-
Publication number: 20080290394Abstract: A nonvolatile memory cell includes a substrate comprising a source, drain, and channel between the source and the drain. A tunnel dielectric layer overlies the channel, and a localized charge storage layer is disposed between the tunnel dielectric layer and a control dielectric layer. A gate electrode has a first surface adjacent to the control dielectric layer, and the first surface includes a midsection and two edge portions. According to one embodiment, the midsection defines a plane, and at least one edge portion extends away from the plane. Preferably, the edge portion extending away from the plane converges toward an opposing second surface of the gate electrode. According to another embodiment, the gate electrode of the nonvolatile memory cell includes a first sublayer and a second sublayer of a different width on the first sublayer.Type: ApplicationFiled: May 15, 2008Publication date: November 27, 2008Inventors: Xiangfeng DUAN, Jian Chen, J. Wallace Parce, Francisco A. Leon
-
Publication number: 20080293244Abstract: Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods.Type: ApplicationFiled: August 5, 2008Publication date: November 27, 2008Applicant: NANOSYS, INC.Inventors: Xiangfeng Duan, Hugh Daniels, Chunming Niu, Vijendra Sahi, James Hamilton, Linda T. Romano
-
Patent number: 7427328Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.Type: GrantFiled: November 21, 2006Date of Patent: September 23, 2008Assignee: Nanosys, Inc.Inventors: Xiangfeng Duan, Chunming Niu, Stephen A. Empedocles, Linda T. Romano, Jian Chen, Vijendra Sahi, Lawrence A. Bock, David P. Stumbo, J. Wallace Parce, Jay L. Goldman
-
Publication number: 20080224123Abstract: The present invention provides methods and systems for nanowire alignment and deposition. Energizing (e.g., an alternating current electric field) is used to align and associate nanowires with electrodes. By modulating the energizing, the nanowires are coupled to the electrodes such that they remain in place during subsequent wash and drying steps. The invention also provides methods for transferring nanowires from one substrate to another in order to prepare various device substrates. The present invention also provides methods for monitoring and controlling the number of nanowires deposited at a particular electrode pair, as well as methods for manipulating nanowires in solution.Type: ApplicationFiled: November 9, 2007Publication date: September 18, 2008Inventors: Samuel Martin, Xiangfeng Duan, Katsumasa Fujii, James M. Hamilton, Hiroshi Iwata, Francisco Leon, Jeffrey Miller, Tetsu Negishi, Hiroshi Ohki, J. Wallace Parce, Cheri X.Y. Pereira, Paul John Schuele, Akihide Shibata, David P. Stumbo, Yasunobu Okada
-
Patent number: 7422980Abstract: Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods.Type: GrantFiled: November 21, 2006Date of Patent: September 9, 2008Assignee: Nanosys, Inc.Inventors: Xiangfeng Duan, R. Hugh Daniels, Chunming Niu, Vijendra Sahi, James M. Hamilton, Linda T. Romano
-
Publication number: 20080200028Abstract: Methods of positioning and orienting nanostructures, and particularly nanowires, on surfaces for subsequent use or integration. The methods utilize mask based processes alone or in combination with flow based alignment of the nanostructures to provide oriented and positioned nanostructures on surfaces. Also provided are populations of positioned and/or oriented nanostructures, devices that include populations of positioned and/or oriented nanostructures, systems for positioning and/or orienting nanostructures, and related devices, systems and methods.Type: ApplicationFiled: November 21, 2006Publication date: August 21, 2008Applicant: Nanosys, Inc.Inventors: Xiangfeng Duan, Hugh Daniels, Chunming Niu, Vijendra Sahi, James Hamilton, Linda T. Romano
-
Publication number: 20080150003Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.Type: ApplicationFiled: December 20, 2006Publication date: June 26, 2008Inventors: Jian Chen, Xiangfeng Duan, Karen Cruden, Chao Liu, Madhuri L. Nallabolu, Srikanth Ranganathan, Francisco Leon, J. Wallace Parce
-
Publication number: 20080150004Abstract: Methods and apparatuses for electronic devices such as non-volatile memory devices are described. The memory devices include a multi-layer control dielectric, such as a double or triple layer. The multi-layer control dielectric includes a combination of high-k dielectric materials such as aluminum oxide (Al2O3), hafnium oxide (HfO2), and/or hybrid films of hafnium aluminum oxide. The multi-layer control dielectric provides enhanced characteristics, including increased charge retention, enhanced memory program/erase window, improved reliability and stability, with feasibility for single or multistate (e.g., two, three or four bit) operation.Type: ApplicationFiled: March 19, 2007Publication date: June 26, 2008Applicant: NANOSYS, INC.Inventors: Jian Chen, Xiangfeng Duan, Karen Cruden, Chao Liu, Madhuri L. Nallabolu, Srikanth Ranganathan, Francisco Leon, J. Wallace Parce
-
Patent number: 7382017Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device.Type: GrantFiled: April 3, 2007Date of Patent: June 3, 2008Assignee: Nanosys, IncInventors: Xiangfeng Duan, Calvin Y. H. Cho, David L. Heald, Chunming Niu, J. Wallace Parce, David P. Stumbo
-
Patent number: 7339184Abstract: The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.Type: GrantFiled: April 29, 2005Date of Patent: March 4, 2008Assignee: Nanosys, IncInventors: Linda T. Romano, Jian Chen, Xiangfeng Duan, Robert S. Dubrow, Stephen A. Empedocles, Jay L. Goldman, James M. Hamilton, David L. Heald, Francesco Lemmi, Chunming Niu, Yaoling Pan, George Pontis, Vijendra Sahi, Erik C. Scher, David P. Stumbo, Jeffery A. Whiteford
-
Publication number: 20080041814Abstract: The present invention is directed to methods to harvest, integrate and exploit nanomaterials, and particularly elongated nanowire materials. The invention provides methods for harvesting nanowires that include selectively etching a sacrificial layer placed on a nanowire growth substrate to remove nanowires. The invention also provides methods for integrating nanowires into electronic devices that include placing an outer surface of a cylinder in contact with a fluid suspension of nanowires and rolling the nanowire coated cylinder to deposit nanowires onto a surface. Methods are also provided to deposit nanowires using an ink-jet printer or an aperture to align nanowires. Additional aspects of the invention provide methods for preventing gate shorts in nanowire based transistors. Additional methods for harvesting and integrating nanowires are provided.Type: ApplicationFiled: August 16, 2007Publication date: February 21, 2008Applicant: NANOSYS, INC.Inventors: Linda Romano, Jian Chen, Xiangfeng Duan, Robert Dubrow, Stephen Empedocles, Jay Goldman, James Hamilton, David Heald, Francesco Lemmi, Chunming Niu, Yaoling Pan, George Pontis, Vijendra Sahi, Erik Scher, David Stumbo, Jeffery Whiteford
-
Publication number: 20080038520Abstract: The present invention is directed to systems and methods for nanowire growth and harvesting. In an embodiment, methods for nanowire growth and doping are provided, including methods for epitaxial oriented nanowire growth using a combination of silicon precursors, as well as us of patterned substrates to grow oriented nanowires. In a further aspect of the invention, methods to improve nanowire quality through the use of sacrifical growth layers are provided. In another aspect of the invention, methods for transferring nanowires from one substrate to another substrate are provided.Type: ApplicationFiled: December 20, 2006Publication date: February 14, 2008Applicant: NANOSYS, Inc.Inventors: Yaoling Pan, Xiangfeng Duan, Robert Dubrow, Jay Goldman, Shahriar Mostarshed, Chunming Niu, Linda Romano, David Stumbo, Alice Fischer-Colbrie, Vijendra Sahi, Virginia Robbins
-
Publication number: 20080032134Abstract: Ligand compositions for use in preparing discrete coated nanostructures are provided, as well as the coated nanostructures themselves and devices incorporating same. Methods for post-deposition shell formation on a nanostructure and for reversibly modifying nanostructures are also provided. The ligands and coated nanostructures of the present invention are particularly useful for close packed nanostructure compositions, which can have improved quantum confinement and/or reduced cross-talk between nanostructures.Type: ApplicationFiled: February 13, 2007Publication date: February 7, 2008Applicant: NANOSYS, Inc.Inventors: Jeffery Whiteford, Rhett Brewer, Mihai Buretea, Jian Chen, Karen Cruden, Xiangfeng Duan, William Freeman, David Heald, Francisco Leon, Chao Liu, Andreas Meisel, Kyu Min, J. Parce, Erik Scher
-
Publication number: 20080026532Abstract: Methods and apparatuses for nanoenabled memory devices and anisotropic charge carrying arrays are described. In an aspect, a memory device includes a substrate, a source region of the substrate, and a drain region of the substrate. A population of nanoelements is deposited on the substrate above a channel region, the population of nanolements in one embodiment including metal quantum dots. A tunnel dielectric layer is formed on the substrate overlying the channel region, and a metal migration barrier layer is deposited over the dielectric layer. A gate contact is formed over the thin film of nanoelements. The nanoelements allow for reduced lateral charge transfer. The memory device may be a single or multistate memory device.Type: ApplicationFiled: September 5, 2007Publication date: January 31, 2008Applicant: NANOSYS, INC.Inventors: Xiangfeng Duan, Calvin Chow, David Heald, Chunming Niu, J. Parce, David Stumbo
-
Publication number: 20070281156Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.Type: ApplicationFiled: March 21, 2006Publication date: December 6, 2007Applicant: President and Fellows of Harvard CollegeInventors: Charles Lieber, Xiangfeng Duan, Yi Cui, Yu Huang, Mark Gudiksen, Lincoln Lauhon, Jianfang Wang, Hongkun Park, Qingqiao Wei, Wenjie Liang, David Smith, Deli Wang, Zhaohui Zhong
-
Patent number: 7301199Abstract: The present invention relates generally to sub-microelectronic circuitry, and more particularly to nanometer-scale articles, including nanoscale wires which can be selectively doped at various locations and at various levels. In some cases, the articles may be single crystals. The nanoscale wires can be doped, for example, differentially along their length, or radially, and either in terms of identity of dopant, concentration of dopant, or both. This may be used to provide both n-type and p-type conductivity in a single item, or in different items in close proximity to each other, such as in a crossbar array. The fabrication and growth of such articles is described, and the arrangement of such articles to fabricate electronic, optoelectronic, or spintronic devices and components.Type: GrantFiled: July 16, 2002Date of Patent: November 27, 2007Assignee: President and Fellows of Harvard CollegeInventors: Charles M. Lieber, Xiangfeng Duan, Yi Cui, Yu Huang, Mark Gudiksen, Lincoln J. Lauhon, Jianfang Wang, Hongkun Park, Qingqiao Wei, Wenjie Liang, David C. Smith, Deli Wang, Zhaohui Zhong