Abstract: Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.

Abstract: Methods for monitoring and improving the fabrication process of integrated circuits using configurable devices are described. In one aspect, the method includes instantiating a test pattern on one or more configurable devices fabricated using the fabrication process, identifying an underperforming region of the configurable devices, and determining if the underperforming region is layout sensitive. At least one of the fabrication process and the layout of the configurable device can then be adjusted based on the determination. In some embodiments, the configurable device may be a programmable logic device, such as a field programmable logic array.

Abstract: Described are methods and circuits for identifying defective device layers and localizing defects. Production PLD tests extract statistically significant data relating failed interconnect resources to the associated conductive metal layer. Failure data thus collected is then analyzed periodically to identify layer-specific problems. Test circuits in accordance with some embodiments employ interconnect resources heavily weighted in favor of specific conductive layers to provide improved layer-specific failure data. Some such test circuits are designed to identify open defects, while others are designed to identify short defects.

Abstract: An improved EEPROM cell with a self-aligned tunneling window is provided which is fabricated by a standard STI process so as to produce a smaller layout size and a reduced cell height. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The length dimension of the floating gate is less than the length dimension of the tunneling window so that the tunneling window is overlapping the floating gate. The tunneling window is self-aligned by edges forming the length dimension of the floating gate so as to form a self-aligned tunneling window.

Abstract: An EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (PMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer having a thickness to allow the electron tunneling across an entire portion of a sense channel upon incurrence of a sufficient voltage potential between a floating gate and the tunnel channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer having a thickness to allow electron tunneling across an entire portion of a tunneling channel upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.

Abstract: An electrically erasable programmable read only memory (EEPROM) comprises a stacked dielectric tunnel oxide region formed between a write transistor and a sense transistor. The tunnel oxide region permits electron tunneling from a floating gate electrode of a sense transistor to the write transistor. The tunnel oxide region includes a first region that has a single dielectric layer optimized for data retention requirements. The tunnel oxide region also includes a second region having a stacked structure optimized for programming speed and comprising a relatively thin first dielectric layer and a second high-K dielectric layer formed thereon.

Abstract: A non-volatile memory cell, comprising a semiconductor substrate having a first conductivity type. A control region is formed of said first conductivity type in the substrate and a control region oxide formed over the control region. The cell includes a program element having a first active region of a second conductivity type formed in said substrate, a doped or implanted region adjacent to said first active region, and a gate oxide overlying at least the channel region. An active region oxide covers a portion of the first active region. A floating gate is formed over said semiconductor substrate on said active region oxide and said control region oxide.

Abstract: An improved EEPROM cell with a self-aligned tunneling window is provided which is fabricated by a standard STI process so as to produce a smaller layout size and a reduced cell height. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The length dimension of the floating gate is less than the length dimension of the tunneling window so that the tunneling window is overlapping the floating gate. The tunneling window is self-aligned by edges forming the length dimension of the floating gate so as to form a self-aligned tunneling window.

Abstract: A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon substrate to form a plurality of isolation regions in the silicon substrate. The isolation trenches are then filled with an oxide layer. The oxide layer and the capping layer are then polished back using techniques known in the art. After polishing, the semiconductor device is annealed between a temperature range of about 1150° C. to about 1200° C.

Abstract: An EEPROM cell is described that is programmed and erased by electron tunneling at separate regions, an edge of a tunneling drain and a sense transistor channel. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer by electron tunneling across an entire portion of a sense channel upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer be electron tunneling at an edge of a tunneling drain upon incurrence of a sufficient voltage potential between the floating gate and the tunneling drain.

Abstract: A two transistor EEPROM cell is described that is erased by electron tunneling across an entire portion of a tunneling channel and programmed by electron tunneling at an edge of a tunneling drain.

Abstract: A method for eliminating source/drain shorting generated during the highly-doped source/drain implant steps in a standard STI process is provided. This is achieved by reducing the RTA temperature to be less than 1000° C. so as to minimize enhanced doping diffusion. Further, the energy level for the highly-doped source/drain implant steps is increased so to compensate for poly depletion in the gate electrodes.

Abstract: A triple-well EEPROM cell is described that is programmed and erased by electron tunneling across an entire portion of separate transistor channels. The EEPROM cell has three transistors formed in a semiconductor substrate. The three transistors are a tunneling transistor (NMOS), a sense transistor (NMOS) and a read transistor (NMOS). The tunneling transistor is formed in a second well (e.g a P conductivity type well) that is separated from the substrate by a first well, having e.g. an N conductivity type. a first well formed in the substrate. Electron tunneling occurs to program the EEPROM cell through a sense tunnel oxide layer upon incurrence of a sufficient voltage potential between a floating gate and the sense channel. Electron tunneling also occurs to erase the EEPROM cell through a tunnel oxide layer upon incurrence of a sufficient voltage potential between the floating gate and the tunneling channel.

Abstract: A semiconductor device having a high reliability passivation includes a planarization layer overlying a multi-level interconnect layer. The passivation layer has a planar surface upon which additional passivation layers are formed. Openings in the overlying passivation layers and the planarization layer expose bonding pads in the multi-level interconnect layer. In a process for fabricating the device, the planarization layer is preferably formed by dispensing a siloxane spin-on-glass (SOG) material onto the surface of the multi-level interconnect layer. The SOG is subsequently planarized to form a substantially planar surface.

Abstract: A process for fabricating a non-volatile memory device includes the step of forming a nitrogen region in a semiconductor substrate prior to carrying out a thermal oxidation process to form a tunnel oxide layer. In a preferred process, nitrogen atoms are ion implanted into a silicon substrate to form a nitrogen region at the substrate surface. Then, a thermal oxidation process is carried out to grow a thin tunnel oxide layer overlying the surface of the nitrogen region. During the oxidation process, nitrogen is incorporated into the growing tunnel oxide layer. A floating-gate electrode is formed overlying the tunnel oxide layer and receives electrical charge transferred from a charge control region of the substrate through the tunnel oxide layer. The tunnel oxide layer is capable of undergoing repeated programming and erasing operations while exhibiting reduced effects from stress induced current leakage.

Abstract: A method of minimizing mechanical stress generated during the trench-forming/trench-filling process steps in a standard shallow trench isolation (STI) process is provided. This is achieved by forming trenches with a more sloped and smoother profile, and/or limiting the trench depth to be less than 0.4 &mgr;m, and/or reducing or increasing the trench densification temperature, and/or performing the densification step after the chemical-mechanical polishing step. In addition, a furnace TEOS oxide film is used as the trench-filling material.

Abstract: A method for fabricating a high-density and high-reliability EEPROM device includes providing a semiconductor substrate having both an EEPROM cell region, and a peripheral MOS transistor region. A gate oxide layer is formed to overlie the peripheral MOS transistor region and the EEPROM cell region. A tunnel oxide region is formed to overlie a portion of the EEPROM cell region. Then, a polycrystalline silicon layer is formed to overlie both the gate oxide layer and the tunnel oxide region. A deuterium annealing process is then carried out to anneal the gate oxide layer and the tunnel oxide region. The polycrystalline silicon layer is patterned to form numerous gate electrodes including gate electrodes for peripheral transistors, floating-gate transistors, and read and write transistors in the EEPROM cell.

Abstract: A non-volatile memory device includes a floating-gate electrode overlying a tunnel oxide layer. A portion of the floating-gate electrode forms the control gate electrode for a sense transistor that is used to determine the presence of charge on the floating-gate electrode. A composite insulation layer overlies the floating-gate electrode. The composite insulation layer includes a dielectric layer, a doped insulating layer overlying the dielectric layer, and a planarization layer overlying the doped insulating layer. The thicknesses of the dielectric layer and the doped insulating layer are precisely determined, such that the doped insulating layer getters mobile ions, such as hydrogen ions, away from the floating-gate electrode, while not capacitively coupling with the floating-gate electrode.

Abstract: A nonvolatile memory device utilizing a program junction region of a p-type impurity and oxide grown thereon. In one aspect, the device comprises a programming structure and a program junction separated from said programming structure by a field oxide region. A program junction oxide layer overlies said program junction region. A floating gate is provided over the oxide which covers said programming structure, said program junction oxide layer, and in some embodiments the gate oxide of a sense transistor.

Abstract: An improved EEPROM cell having a field-edgeless tunnel window is provided which is fabricated by a STI process so as to produce reliable endurance and data retention. The EEPROM cell includes a floating gate, a programmable junction region, and a tunneling oxide layer separating the programmable junction region and the floating gate. The tunneling oxide layer defines a tunnel window which allows for programming and erasing of the floating gate by tunneling electrons therethrough. The programmable junction region has a width dimension and a length dimension so as to define a first area. The tunnel window has a width dimension and a length dimension so as to define a second area. The second area of the tunnel window is completely confined within the first area of the programmable junction region so as to form a field-edgeless tunnel window.