Abstract: A method of fabricating a semiconductor device is described. The method includes forming a nanosheet stack on a substrate, the nanosheet stack includes nanosheet channel layers. A gate is formed around the nanosheet channel layers of the nanosheet stack. A strained material is formed along a sidewall surface of the gate. The strained material is configured to create strain in the nanosheet channel layers of the nanosheet stack.

Abstract: Methods and apparatuses are provided for movie and television series video data analysis. The method includes: gathering and reading, by a processor, a plurality of input movies; removing a video border of each input movie; splitting the input movie into short clips, based on accuracy and efficiency requirements of different analyzing models; assessing attributes of each input movie by analyzing, with the different analyzing models, the input movie, the short clips cut from the input movie, and the frame images extracted from the input movie; and summarizing the plurality of input movies based on matching and integrating the attributes assessed for each input movie.

Abstract: Methods and apparatuses are provided for movie and television series video data analysis. The method includes: gathering and reading, by a processor, a plurality of input movies; removing a video border of each input movie; splitting the input movie into short clips, based on accuracy and efficiency requirements of different analyzing models; assessing attributes of each input movie by analyzing, with the different analyzing models, the input movie, the short clips cut from the input movie, and the frame images extracted from the input movie; and summarizing the plurality of input movies based on matching and integrating the attributes assessed for each input movie.

Abstract: A semiconductor device including a plurality of nanosheet transistor channels adjacent to a source/drain. An inner spacer located between each of the plurality of nanosheet transistor channels and the inner spacer wraps around the end of each of the plurality of nanosheet transistors. The source/drain is in contact with the inner spacer and each of the plurality of nanosheet transistor channels. A gate surrounding each of the plurality of nanosheet transistor channels and an electrical contact connected to the source/drain. An ultra low-k spacer located between the gate and the source/drain. The ultra low-k spacer reduces the parasitic capacitance of the nanosheet transistor.

Abstract: The disclosure provides methods for characterizing a target DNA present in a sample. The methods involve contacting the sample with one or more universal primers to amplify target DNA; contacting the amplified target DNA with a type V CRISPR/Cas effector protein and one or more guide RNAs, where the contacting generates a cleavage product comprising a 5? overhang; and ligating a double-stranded nucleic acid adapter to the cleavage product, to generate a ligation product. The ligation product includes the target DNA, which can be sequenced. The sample can be subjected to one or more amplification steps prior to the contacting step, with primers that provide for amplification of nucleic acids of, e.g., specific pathogens, categories of pathogens, two or more different pathogens, or two or more different categories of pathogens.

Abstract: Disclosed herein are systems and methods for providing a high-throughput DETECTR assay in a single chamber. The single chamber may be one well of a microplate, and multiple assays may be conducted in a staggered fashion in separate chambers. The methods described herein implement a process including lysing a sample, isolating nucleic acid molecules, eluting the nucleic acid molecules, amplifying the nucleic acid molecules, and detecting a presence of a target nucleic acid.

Abstract: Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes performing fabrication operations that form the IC. The fabrication operations include forming a channel fin. A gate structure is formed along a sidewall surface of the channel fin. The gate structure includes a conductive gate having an L-shape profile, and the L-shape profile includes a conductive gate foot region. The conductive gate foot region is replaced with a dielectric foot region.

Abstract: The subject disclosure relates to high mobility complementary metal-oxide-semiconductor (CMOS) devices and techniques for forming the CMOS devices with fins formed directly on the insulator. According to an embodiment, a method for forming such a high mobility CMOS device can comprise forming, via a first epitaxial growth of a first material, first pillars within first trenches formed within a dielectric layer, wherein the dielectric layer is formed on a silicon substrate, and wherein the first pillars comprise first portions with defects and second portions without the defects. The method can further comprise forming second trenches within a first region of the dielectric layer, and further forming second pillars within the second trenches via a second epitaxial growth of one or more second materials using the second portions of the first pillars as seeds for the second epitaxial growth.

Abstract: A method of forming a vertical fin field effect transistor device is provided. The method includes forming a vertical fin and fin template on a bottom source/drain layer, wherein the fin template is on the vertical fin. The method further includes forming a gate structure on the vertical fin and fin template, and forming a top spacer layer on the gate structure. The method further includes removing the fin template to form an opening in the top spacer layer, and removing a portion of a gate electrode of the gate structure to form a cavity; and removing a portion of a gate dielectric layer of the gate structure to form a groove around the vertical fin.

Abstract: A nanosheet device includes a bottom dielectric isolation formed by a first portion of a high-k dielectric layer above a semiconductor substrate, a spacer material above the first portion of the high-k dielectric layer and a second portion of the high-k dielectric layer above the spacer material. A sequence of semiconductor channel layers are stacked perpendicularly to the semiconductor substrate above the bottom dielectric isolation and are separated by and vertically aligned with a metal gate stack. Source/drain regions extend laterally from opposite ends of the semiconductor channel layers with a bottom surface of the source/drain regions being in direct contact with the bottom dielectric isolation for electrically isolating the source/drain regions from the semiconductor substrate.

Abstract: Computer systems, service processing methods, and chips are provided in this disclosure. In one implementation, a computer system comprises an interrupt status register, a permission management register, a processor, a target storage space, and a memory storing programming instructions for execution by the processor to: set a flag corresponding to the first interrupt in the interrupt status register to a first interrupt flag and a flag corresponding to the first interrupt in the permission management register to a first call flag, wherein the first interrupt flag and the first call flag indicate whether access to the target storage space is allowed, determine whether to allow the processor to access the target storage space, and obtain first information in the target storage space in a TEE mode if determining that the processor is allowed to access the target storage space; and execute the target service based on the first information.

Abstract: A method for manufacturing a semiconductor device includes forming a source layer on a semiconductor substrate, forming a channel layer on the source layer, and forming a drain layer on the channel layer. The source, channel and drain layers are patterned into at least one fin, and a cap layer is formed on a lower portion of the at least one fin. The lower portion of the at least one fin includes the source layer and part of the channel layer. The method further includes forming a gate structure comprising a gate dielectric layer and a gate conductor on the at least one fin and on the cap layer. The cap layer is positioned between the lower portion of the at least one fin and the gate dielectric layer.

Abstract: A vertical field-effect transistor includes a substrate comprising a semiconductor material; a first set of fins formed from the semiconductor material and extending vertically with respect to the substrate; and a second set of fins extending vertically with respect to the substrate, wherein ones of the second set of fins abut ones of the first set of fins. The second set of fins comprises a dielectric material.

Abstract: Vertical transport field-effect transistors are formed on active regions wherein the active regions each include a wrap-around metal silicide contact on vertically extending side walls of the active region. Such wrap-around contacts form self-aligned and reliable strapping for SRAM bottom nFET and pFET source/drain regions. Buried contacts of SRAM cells may be used to strap the wrap-around metal silicide contacts with the gates of inverters thereof. Wrap-around metal silicide contacts provide additional contacts for logic FETs and reduce parasitic bottom source/drain resistance.

Abstract: The present disclosure is directed to the use of a compound of Formula (III) in the treatment of malignancies.

Abstract: Described herein are devices, systems, fluidic devices, kits, and methods for detection of target nucleic acids associated with diseases, cancers, genetic disorders, a genotype, a phenotype, or ancestral origin. The devices, systems, fluidic devices, kits, and methods may comprise reagents of a guide nucleic acid targeting a target nucleic acid, a programmable nuclease, and a single stranded detector nucleic acid with a detection moiety. The target nucleic acid of interest may be indicative of a disease, and the disease may be communicable diseases, or of a cancer or genetic disorder. The target nucleic acid of interest may be indicative of a genotype, a phenotype, or ancestral origin.

Abstract: A semiconductor device comprising a plurality of nanosheet transistor channels adjacent to a source/drain. An inner spacer located between each of the plurality of nanosheet transistor channels and the inner spacer wraps around the end of each of the plurality of nanosheet transistors, wherein the source/drain is in contact with the inner spacer and each of the plurality of nanosheet transistor channels. A gate surrounding each of the plurality of nanosheet transistor channels and an electrical contact connected to the source/drain. An ultra low-k spacer located between the gate and the source/drain, wherein the ultra low-k spacer reduces the parasitic capacitance of the nanosheet transistor.

Abstract: A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess.

Abstract: A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of first type sacrificial layers and active semiconductor layers. The method includes forming the first type sacrificial layer on sidewalls of the nanosheet stacks, then forming a dielectric pillar between the sidewall portions of the first type sacrificial layers of adjacent nanosheet stacks, and then removing the first type sacrificial layer. The method also includes forming a PWFM layer in spaces formed by the removal of the first type sacrificial layer for a first one of the nanosheet stacks, and includes forming a NWFM layer in spaces formed by the removal of the first type sacrificial layer for an adjacent second one of the nanosheet stacks.

Abstract: A method of forming a vertical fin field effect device is provided. The method includes, forming a vertical fin on a substrate, forming a masking block on the vertical fin, wherein the masking block extends a distance outward from the vertical fin sidewalls and endwalls, and a portion of the substrate surrounding the masking block is exposed. The method further includes removing at least a portion of the exposed portion of the substrate to form a recess and a fin mesa below the vertical fin, removing a portion of the fin mesa to form an undercut recess below an overhanging portion of the masking block, forming a spacer layer on the masking block and in the undercut recess, and removing a portion of the spacer layer to form an undercut spacer in the undercut recess.