Abstract: A method and an apparatus for training a generative adversarial network (GAN) and a method and an apparatus for processing an image are provided. The method for training the GAN includes: obtaining a fine-grained style label (FGSL) associated with the image and inputting the FGSL and a latent vector into a style-based generator in the GAN; the style-based generator generating an first output image based on the FGSL and the latent vector; the projection discriminator determining whether the first output image matches the image based on the FGSL; and adjusting one or more parameters of the GAN and regenerating, by the style-based generator, a second output image based on the FGSL, the latent vector, and the adjusted GAN in response to determining that the first output image does not match the image based on the FGSL.

Abstract: Described herein are devices, systems, fluidic devices, kits, and methods for detection of target nucleic acids.

Abstract: A method for fabricating a stacked nanopore includes forming a stack of layers having alternating conductive lines and dielectric layers on a substrate, and patterning the stack to form a staircase structure with the conductive lines having a length gradually changing at each level in the stack. The method also includes depositing and planarizing a dielectric material over the staircase structure, forming contacts through the dielectric material to the conductive lines for each level of conductive lines, etching a nanopore through the stack of layers to form pairs of opposing electrodes across the nanopore using the conductive lines; and opening up the substrate to expose the nanopore.

Abstract: Techniques for controlling top spacer thickness in VFETs are provided. In one aspect, a method of forming a VFET device includes: depositing a dielectric hardmask layer and a fin hardmask(s) on a wafer; patterning the dielectric hardmask layer and the wafer to form a fin(s) and a dielectric cap on the fin(s); forming a bottom source/drain at a base of the fin(s); forming bottom spacers on the bottom source/drain; forming a gate stack alongside the fin(s); burying the fin(s) in a dielectric fill material; selectively removing the fin hardmask(s); recessing the gate stack to form a cavity in the dielectric fill material; depositing a spacer material into the cavity; recessing the spacer material to form top spacers; removing the dielectric cap; and forming a top source/drain at a top of the fin(s). A VFET device is also provided.

Abstract: A semiconductor structure may include a bottom source drain, a top source drain, a gate stack. The top source drain is above the gate stack and the bottom source drain is below the gate stack. The semiconductor structure may also include a bottom spacer and a top spacer. The gate stack is between the bottom spacer and the top spacer. The bottom spacer and the top spacer each comprise a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the top source drain, and the bottom source drain.

Abstract: A travelling-type tunnel hard-rock micro-damage cutting equipment and a construction method associated therewith are provided. The cutting equipment includes: a crawler-type trolley; and a hard-rock drilling construction apparatus, a hard-rock cutting construction apparatus, a self-unloading tipping bucket and a visual operation terminal all arranged on the crawler-type trolley. The hard-rock cutting construction apparatus includes: a cutting manipulation room, a rock-breaking power arm, and a hard-rock cutting device including a hydraulic steel robs, a signal sensor, an infrared lens and a light source assembly. The infrared lens and the light source assembly are arranged at the front end of the hard-rock cutting device, and a working image can be transmitted to the visual operation terminal through the signal sensor. The cutting equipment can accurately and efficiently cut a rock mass, and the cut rock mass can be reused according to secondary processing conditions of rock to improve economic benefits.

Abstract: A fork-sheet semiconductor device includes a first-type source/drain region on a substrate and a second-type source/drain region on the substrate and separated from the first-type source/drain region by an insulator pillar. The fork-sheet semiconductor device further includes a first metal portion and a second metal portion. The first metal portion completely covers a first upper surface and a first exposed sidewall the first-type source/drain region and the second metal portion completely covers a second upper surface and a second exposed sidewall the second-type source/drain region. The first and second metal portions are separated from one another by the insulator pillar. A first-type contact portion extends vertically from the first metal portion and an opposing second-type contact portion extends vertically from the second metal portion. A first upper interconnect structure contacts the first-type contact portion and a second upper interconnect structure contacts the second-type contact portion.

Abstract: A method of manufacturing a nanosheet field effect transistor (FET) device is provided. The method includes forming a plurality of nanosheet stacks on a substrate, the nanosheet stacks including alternating layers of first type sacrificial layers and active semiconductor layers. The method includes forming the first type sacrificial layer on sidewalls of the nanosheet stacks, then forming a dielectric pillar between the sidewall portions of the first type sacrificial layers of adjacent nanosheet stacks, and then removing the first type sacrificial layer. The method also includes forming a PWFM layer in spaces formed by the removal of the first type sacrificial layer for a first one of the nanosheet stacks, and includes forming a NWFM layer in spaces formed by the removal of the first type sacrificial layer for an adjacent second one of the nanosheet stacks.

Abstract: A semiconductor structure may include a bottom source drain, a top source drain, a gate stack. The top source drain is above the gate stack and the bottom source drain is below the gate stack. The semiconductor structure may also include a bottom spacer and a top spacer. The gate stack is between the bottom spacer and the top spacer. The bottom spacer and the top spacer each comprise a dipole liner. The dipole liner includes a first layer and a second layer. The second layer may be in direct contact with the first layer. The second layer may be made of different material than the first layer. The first layer may be made of silicon oxide. The second layer may be made of silicon nitride or aluminum oxide. The first layer may be in direct contact with the gate stack, the top source drain, and the bottom source drain.

Abstract: Systems and methods for taking into account susceptibility deviations in magnetic-resonance-based therapy planning by a magnetic resonance tomography unit. A B0 field map is determined by the magnetic resonance tomography unit. A location blur distribution is determined from the B0 field map and from the location blur distribution in turn, a parameter of an image acquisition as a function of the location blur distribution, in such a way that an image acquisition brings about a reduced location blur with the determined parameter.

Abstract: A method is presented for reducing sagging effects in nanosheet devices. The method includes forming at least two nanosheet structures over a substrate, wherein each nanosheet structure includes alternating layers of a first semiconductor material and a second semiconductor material, depositing a dielectric layer over the at least two nanosheet structures, depositing a dummy gate over the dielectric layer, etching the first semiconductor material to create voids filled with inner spacers, removing the dummy gate and the dielectric layer such that a supporting dielectric section remains between the at least two nanosheet structures, and removing the etched first semiconductor material such that a supporting structure is defined including the supporting dielectric section and the second semiconductor material.

Abstract: Embodiments of the invention include a method for fabricating a semiconductor device and the resulting structure. A nanosheet stack of alternating nanosheets of a sacrificial semiconductor material and a semiconductor channel material located on a substrate is provided. An additional dielectric spacer is formed on the dielectric spacer and within a gap. Dielectric spacer is removed. An epitaxial oxide layer is formed on the re-exposed recessed surfaces of the substrate. Germanium is formed on the epitaxial oxide layer. Sidewalls of each semiconductor channel material nanosheet are physically exposed. A source/drain is formed on a surface of the germanium. ILD material is formed above each source/drain and above an adjacent region. Portions of ILD material are removed such that sidewalls of the source/drain and germanium are exposed. The germanium is removed. A contact region is formed that wraps around the source/drain region.

Abstract: Described herein are devices, systems, fluidic devices, kits, and methods for detection of target nucleic acids associated with diseases, cancers, genetic disorders, a genotype, a phenotype, or ancestral origin. The devices, systems, fluidic devices, kits, and methods may comprise reagents of a guide nucleic acid targeting a target nucleic acid, a programmable nuclease, and a single stranded detector nucleic acid with a detection moiety. The target nucleic acid of interest may be indicative of a disease, and the disease may be communicable diseases, or of a cancer or genetic disorder. The target nucleic acid of interest may be indicative of a genotype, a phenotype, or ancestral origin.

Abstract: A semiconductor device is provided. The semiconductor device includes an n-doped field effect transistor (nFET) section, a p-doped field effect transistor (pFET) section and an insulator pillar. The nFET section includes nFET nanosheets and nFET source or drain (S/D) regions partially surrounding the nFET nanosheets. The pFET section includes pFET nanosheets and pFET S/D regions partially surrounding the pFET nanosheets. The insulator pillar is interposed between the nFET S/D regions and the pFET S/D regions to form a fork-sheet structure with the nFET nanosheets and the pFET nanosheets.

Abstract: Described herein are devices, systems, fluidic devices, kits, and methods for detection of target nucleic acids associated with diseases, cancers, genetic disorders, a genotype, a phenotype, or ancestral origin. The devices, systems, fluidic devices, kits, and methods may comprise reagents of a guide nucleic acid targeting a target nucleic acid, a programmable nuclease, and a single stranded detector nucleic acid with a detection moiety. The target nucleic acid of interest may be indicative of a disease, and the disease may be communicable diseases, or of a cancer or genetic disorder. The target nucleic acid of interest may be indicative of a genotype, a phenotype, or ancestral origin.

Abstract: Described herein are devices, systems, fluidic devices, kits, and methods for detection of target nucleic acids associated with diseases, cancers, genetic disorders, a genotype, a phenotype, or ancestral origin. The devices, systems, fluidic devices, kits, and methods may comprise reagents of a guide nucleic acid targeting a target nucleic acid, a programmable nuclease, and a single stranded detector nucleic acid with a detection moiety. The target nucleic acid of interest may be indicative of a disease, and the disease may be communicable diseases, or of a cancer or genetic disorder. The target nucleic acid of interest may be indicative of a genotype, a phenotype, or ancestral origin.

Abstract: Forming a fin, where the fin includes a nanowire stack on a semiconductor substrate, where the nanowire stack includes a plurality of silicon layers and a plurality of silicon germanium layers stacked one on top of the other in an alternating fashion, removing a portion of the fin to form an opening and expose vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layer, and epitaxially growing a source drain region/structure in the opening from the exposed vertical sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers, where the source drain region/structure substantially fills the opening.

Abstract: FET devices with bottom dielectric isolation and sidewall implants in the source and drain regions to prevent epitaxial growth below the bottom dielectric isolation are provided. In one aspect, a semiconductor FET device includes: a device stack(s) disposed on a substrate, wherein the device stack(s) includes active layers oriented vertically over a bottom dielectric isolation layer; STI regions embedded in the substrate at a base of the device stack(s), wherein a top surface of the STI regions is recessed below a top surface of the substrate exposing substrate sidewalls under the bottom dielectric isolation region, wherein the sidewalls of the substrate include implanted ions; source and drains on opposite sides of the active layers; and gates surrounding a portion of each of the active layers, wherein the gates are offset from the source and drains by inner spacers. A method of forming a semiconductor FET device is also provided.

Abstract: A vertical field effect transistor (VFET) has a top source/drain (S/D) with a first region having a first area and a first capacitance and a second region having a second area and a second capacitance. A first top spacer on a gate cross section area. A second top spacer with a varying thickness is disposed the first top spacer. Both the first and second top spacers are between the top S/D and the gate cross section area. Due to the varying thickness of the second spacer with the smaller thickness closer to the fin, the separation distance between the larger, first area and the gate cross section area is greater than the separation distance between the smaller, second area and the gate cross section area. Therefore, the first capacitance is reduced because of the larger separation distance and the second capacitance is reduced because of the smaller second area.

Abstract: A method of forming a vertical transport field-effect transistor (VFET) is provided. The method includes forming vertical fin channels by etching part way through a substrate. The method further includes forming a bottom source/drain electrode partially into the substrate and beneath the vertical fin channels. A gate dielectric layer is then formed on the vertical fin channels. A gate conductor layer is then formed on the gate dielectric layer. A height of the gate conductor layer is less than a height of the vertical fin channels. The method further includes forming a spacer layer on a top surface of the gate conductor layer. The method also includes forming a top source/drain electrode on a top surface of the vertical fin channels. A gap exists between the top source/drain electrode and the spacer layer.