Abstract: A non-volatile memory system includes a plurality of non-volatile data memory cells arranged into groups of data memory cells, a plurality of select devices connected to the groups of data memory cells, a selection line connected to the select devices, a plurality of data word lines connected to the data memory cells, and one or more control circuits connected to the selection line and the data word lines. The one or more control circuits are configured to determine whether the select devices are corrupted. If the select devices are corrupted, then the one or more control circuits repurpose one of the word lines (e.g., the first data word line closet to the select devices) to be another selection line, thus operating the memory cells connected to the repurposed word line as select devices.

Abstract: A soft information module is coupled between one or more flash memory devices and a decoder. The soft information module receives a putative value of one or more memory cells of the one or more flash memory devices based on a read of the one or more memory cells at an initial read level, and one or more respective indicators of whether the putative value was read at one or more respective different read levels offset from the initial read level, and receives a page indicator for the read. The soft information module determines a cell program region for the read based on the putative value, the one or more respective indicators, and the page indicator, identifies a predetermined confidence value for the region, and provides the confidence value to the decoder for association with the putative value, the confidence value being representative of a likelihood that the one or more memory cells was programmed to the putative value.

Abstract: A data storage device includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller is configured, based on a metric associated with a portion of the non-volatile memory, to store a read technique indicator that indicates that the portion is to be read using a high-reliability read technique.

Abstract: A non-volatile memory system includes a plurality of non-volatile data memory cells arranged into groups of data memory cells, a plurality of select devices connected to the groups of data memory cells, a selection line connected to the select devices, a plurality of data word lines connected to the data memory cells, and one or more control circuits connected to the selection line and the data word lines. The one or more control circuits are configured to determine whether the select devices are corrupted. If the select devices are corrupted, then the one or more control circuits repurpose one of the word lines (e.g., the first data word line closet to the select devices) to be another selection line, thus operating the memory cells connected to the repurposed word line as select devices.

Abstract: Technology is described for selecting a group of reversible-resistance memory cells in which to store data based on information regarding switching the reversible-resistance memory cells from a first resistance state in which the reversible-resistance memory cells are in immediately after fabrication to a second resistance state for the first time after fabrication. Information regarding switching the reversible-resistance memory cells from the first resistance state to the second resistance state for the first time after fabrication may provide insight into factors including, but not limited to, endurance and data retention. In one aspect, a control circuit is configured to select a group of reversible-resistance memory cells in which to store data based on both the difficulty in switching from the first resistance state to the second resistance state for the first time after fabrication and a temperature of the data to be stored in the memory system.

Abstract: A data storage device includes a memory. A method includes de-allocating a first region of a group of regions of the memory during a wear leveling process based on a determination that the first region is associated with a first tag of a set of tags. Each region of the group of regions is assigned to a tag of the set of tags based on a health metric associated with the region. The health metric is based on a bit error rate (BER), a program/erase cycle (PEC) count, a PEC condition metric, or a combination thereof. In response to selecting the first region, information is copied from the first region to a second region of the memory during the wear leveling process.

Abstract: A data storage device includes a controller and a non-volatile memory coupled to the controller. The controller is configured to generate first parity information based on first data and to generate second parity information based on second data. The non-volatile memory is configured to store the first data and the second data. The data storage device also includes a buffer configured to store the first parity information. The controller is further configured to generate joint parity information associated with the first data and the second data in response to a combined data size of the first data and the second data satisfying a threshold.

Abstract: Systems and methods for metablock relinking may be provided. A first physical block of a first metablock may be determined to have a different health than a second physical block of a second metablock based on health indicators of the first and second physical blocks. Each of the health indicators may indicate an extent to which a respective one of the first and second physical blocks may be written to and/or erased before the respective one of the first and second physical blocks becomes defective. The first physical block of the first metablock may be replaced with the second physical block of the second metablock based on a determination that the health of the first physical block of the first metablock is different than the health of the second physical block of the second metablock.

Abstract: A data storage device includes a controller and a non-volatile memory coupled to the controller. The controller is configured to generate first parity information based on first data and to generate second parity information based on second data. The non-volatile memory is configured to store the first data and the second data. The data storage device also includes a buffer configured to store the first parity information. The controller is further configured to generate joint parity information associated with the first data and the second data in response to a combined data size of the first data and the second data satisfying a threshold.

Abstract: A storage device with a memory may include memory block leveling that improves data retention by considering localized temperature. A block's distance from a heat source may result in variance of data retention. The localized temperature may be used to improve data retention through a relocation, refreshing, or leveling of blocks that considers their physical location on the die and/or in the package.

Abstract: Systems, apparatuses, and methods are provided that dynamically reassign counters (or other memory monitors) in a memory. A plurality of counters may be assigned to different address ranges within an overall address range of a memory. The value of the counter may be indicative of activity, such as reads, within a respective assigned address range. Depending on the value of the counter, the respective address range of the counter may be dynamically changed. For example, a counter with a high value (indicating higher activity within the address range) may have its respective address range divided, with two counters being assigned to each of the divided address ranges. Likewise, counters with low values (indicating less activity within the address ranges) may have their respective address ranges combined, with a single counter being assigned to the combined address ranges.

Abstract: Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.

Abstract: Systems and methods for controlling blocks in a memory device using a health indicator (such as the failed bit count) for the blocks are disclosed. However, the health indicator may exhibit noise, thereby resulting in an unreliable indicator of the health of the blocks in the memory device. In order to filter out the noise, a rolling average of the health indicator may be determined, and compared to the current health indicator. The comparison with the rolling average may indicate whether the current health indicator is an outlier, and thus should not be used. The health indicator may also be used to predict a future health indicator for different blocks in the memory device. Using the predicted future health indicator, the use of the blocks may be changed in order to more evenly wear the blocks.

Abstract: A data storage device includes a memory. A method includes de-allocating a first region of a group of regions of the memory during a wear leveling process based on a determination that the first region is associated with a first tag of a set of tags. Each region of the group of regions is assigned to a tag of the set of tags based on a health metric associated with the region. The health metric is based on a bit error rate (BER), a program/erase cycle (PEC) count, a PEC condition metric, or a combination thereof. In response to selecting the first region, information is copied from the first region to a second region of the memory during the wear leveling process.

Abstract: A data storage device includes a non-volatile memory. The non-volatile memory may include a first word line, a second word line, and a third word line. The second word line may be between the first word line and the third word line. The non-volatile memory may further include a first string and a second string. The first string may be adjacent to the second string. The data storage device may further include circuitry configured to store parity information at a fourth word line of the non-volatile memory. The parity information may correspond to a combination of first data associated with the first word line and the first string, second data associated with the first word line and the second string, third data associated with the third word line and the first string, and fourth data associated with the third word line and the second string.

Abstract: Decoding logic is provided that is operational upon a data buffer to represent a plurality of variable nodes and a plurality of check nodes. For a respective one of the variable nodes, a vector component is selected from a confidence vector associated with the variable node. Using a respective one of the check nodes, a check node return value is calculated based on one or more other vector components from one or more other vectors and one or more vector indices corresponding to the one or more other vector components. The confidence vector is then updated based on the check node return value and an index for the check node return value, and a current state of a memory cell associated with the respective one of the variable nodes is determined based on a location of a primary one of multiple vector components within the updated confidence vector.

Abstract: Systems, apparatuses, and methods are provided that dynamically reassign counters (or other memory monitors) in a memory. A plurality of counters may be assigned to different address ranges within an overall address range of a memory. The value of the counter may be indicative of activity, such as reads, within a respective assigned address range. Depending on the value of the counter, the respective address range of the counter may be dynamically changed. For example, a counter with a high value (indicating higher activity within the address range) may have its respective address range divided, with two counters being assigned to each of the divided address ranges. Likewise, counters with low values (indicating less activity within the address ranges) may have their respective address ranges combined, with a single counter being assigned to the combined address ranges.

Abstract: Disclosed is a system and method for reading flash memory cells with dynamically adjusted probability values (e.g., log-likelihood ratios). In connection with reading bit values from flash memory cells, one or more predetermined first probability values are adjusted relative to one or more predetermined second probability values. The one or more predetermined first probability values are associated with reading one or more memory cells programmed to a first binary value, and the one or more predetermined second probability values are associated with reading one or more memory cells programmed to a second binary value. The plurality of bit values read from the plurality of non-volatile memory cells and the one or more adjusted first probability values are provided to a decoder for use in decoding the plurality of bit values.

Abstract: Systems and methods for metablock relinking may be provided. A first physical block of a first metablock may be determined to have a different health than a second physical block of a second metablock based on health indicators of the first and second physical blocks. Each of the health indicators may indicate an extent to which a respective one of the first and second physical blocks may be written to and/or erased before the respective one of the first and second physical blocks becomes defective. The first physical block of the first metablock may be replaced with the second physical block of the second metablock based on a determination that the health of the first physical block of the first metablock is different than the health of the second physical block of the second metablock.

Abstract: A data storage device includes a memory having a three-dimensional (3D) memory configuration. A method includes writing first data at a first physical page that is disposed within the memory at a first distance from a substrate of the memory. The first data is written at the first physical page using a first write technique. The method further includes writing second data at a second physical page that is disposed within the memory at a second distance from the substrate. The second distance is greater than the first distance. The second data is written at the second physical page using a second write technique that is different than the first write technique.