Patents by Inventor Yacov Duzly
Yacov Duzly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10635599Abstract: An apparatus includes a storage controller, a non-volatile memory die comprising a set of memory elements and a memory die controller associated with the non-volatile memory die. The memory die controller is configured to identify a portion of the non-volatile memory die for mapping logical addresses, read a header of a sub-portion of the identified portion, for a logical address, map a physical address corresponding to the logical address of the sub-portion to a physical-to-logical mapping and transmit the physical-to-logical mapping to the storage controller.Type: GrantFiled: July 26, 2018Date of Patent: April 28, 2020Assignee: SanDisk Technologies LLCInventors: Yacov Duzly, Yan Li, Idan Alrod
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Patent number: 10572169Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.Type: GrantFiled: January 22, 2018Date of Patent: February 25, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Marina Frid, Igor Genshaft, Einat Inna Zevulun, Yacov Duzly, Amir Shaharabany
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Publication number: 20200034307Abstract: An apparatus includes a storage controller, a non-volatile memory die comprising a set of memory elements and a memory die controller associated with the non-volatile memory die. The memory die controller is configured to identify a portion of the non-volatile memory die for mapping logical addresses, read a header of a sub-portion of the identified portion, for a logical address, map a physical address corresponding to the logical address of the sub-portion to a physical-to-logical mapping and transmit the physical-to-logical mapping to the storage controller.Type: ApplicationFiled: July 26, 2018Publication date: January 30, 2020Inventors: Yacov DUZLY, Yan LI, Idan ALROD
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Patent number: 10296260Abstract: A method and system for write amplification analysis are provided. In one embodiment, a method is provided that is performed in a computing device. The method comprises determining an amount of data written from the computing device to a storage system over a time period, wherein the storage system comprises a memory; determining an amount of data written to the memory by the storage system over the time period; calculating a write amplification factor over the time period; and simultaneously displaying graphs of the amount of data written from the computing device over the time period, the amount of data written to the memory over the time period, and the write amplification factor over the time period. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: GrantFiled: November 9, 2016Date of Patent: May 21, 2019Assignee: SanDisk Technologies LLCInventors: Yacov Duzly, Eyal Sobol, Tal Shaked, Liat Hod, Omer Gilad, Zevulun Einat Inna
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Patent number: 10289557Abstract: A storage system and method for fast lookup in a table-caching database are provided. In one embodiment, a storage system is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to store, in the volatile memory, a data structure representing a compressed version of a logical-to-physical address table stored in the non-volatile memory; and search the data structure for a physical address associated with a logical address, wherein the controller is configured to find any physical address in the data structure in a fixed amount of time. Other embodiments are provided.Type: GrantFiled: August 28, 2017Date of Patent: May 14, 2019Assignee: Western Digital Technologies, Inc.Inventors: Yacov Duzly, Hadas Oshinsky
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Patent number: 10289327Abstract: A method that may be performed by a data storage device includes configuring the data storage device to use a first scheduling scheme and, in response to detecting a trigger event, configuring the data storage device to use a second scheduling scheme. One of the first scheduling scheme and the second scheduling scheme is used to schedule performance of memory operations having the same operation type at a plurality of dies of a memory of the data storage device. The other of the first scheduling scheme and the second scheduling scheme is used to schedule memory operations opportunistically.Type: GrantFiled: June 24, 2015Date of Patent: May 14, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Einat Inna Zevulun, Yacov Duzly, Amir Shaharabany, Igor Genshaft, Marina Frid
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Publication number: 20190065387Abstract: A storage system and method for fast lookup in a table-caching database are provided. In one embodiment, a storage system is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to store, in the volatile memory, a data structure representing a compressed version of a logical-to-physical address table stored in the non-volatile memory; and search the data structure for a physical address associated with a logical address, wherein the controller is configured to find any physical address in the data structure in a fixed amount of time. Other embodiments are provided.Type: ApplicationFiled: August 28, 2017Publication date: February 28, 2019Applicant: Western Digital Technologies, Inc.Inventors: Yacov Duzly, Hadas Oshinsky
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Patent number: 10126970Abstract: Systems, methods and/or devices are used to pair metablocks in a non-volatile storage device. In one aspect, a method of data organization of a memory device includes, writing data to and reading data from respective metablocks in a set of metablocks. The method further includes while performing said writing and reading: (1) accessing one or more management data structures in controller memory, identifying two or more metablock pairs; (2) accessing and updating metablock status information indicating which metablocks of the set of metablocks are closed, free and open; and (3) accessing and updating a valid count, corresponding to a number of sub-block memory units having valid data for each of a plurality of metablocks in the set of metablocks.Type: GrantFiled: November 10, 2016Date of Patent: November 13, 2018Assignee: SanDisk Technologies LLCInventors: Amir Shaharabany, Hadas Oshinsky, Yacov Duzly, James Fitzpatrick
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Patent number: 10114743Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to maintain a first address translation table associated with the memory and a second address translation table associated with the memory. The controller is further configured to receive a command to erase the memory. The controller is further configured to switch an indicator of an active address translation table from the first address translation table to the second address translation table in response to receiving the command.Type: GrantFiled: April 6, 2016Date of Patent: October 30, 2018Assignee: SANDISK TECHNOLOGIES INC.Inventors: Tal Heller, Asaf Garfunkel, Hadas Oshinsky, Yacov Duzly, Amir Shaharabany, Judah Gamliel Hahn
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Publication number: 20180143779Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.Type: ApplicationFiled: January 22, 2018Publication date: May 24, 2018Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: MARINA FRID, IGOR GENSHAFT, EINAT INNA ZEVULUN, YACOV DUZLY, AMIR SHAHARABANY
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Publication number: 20180129448Abstract: A method and system for write amplification analysis are provided. In one embodiment, a method is provided that is performed in a computing device. The method comprises determining an amount of data written from the computing device to a storage system over a time period, wherein the storage system comprises a memory; determining an amount of data written to the memory by the storage system over the time period; calculating a write amplification factor over the time period; and simultaneously displaying graphs of the amount of data written from the computing device over the time period, the amount of data written to the memory over the time period, and the write amplification factor over the time period. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.Type: ApplicationFiled: November 9, 2016Publication date: May 10, 2018Applicant: SanDisk Technologies LLCInventors: Yacov Duzly, Eyal Sobol, Tal Shaked, Liat Hod, Omer Gilad, Zevulun Einat Inna
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Patent number: 9940039Abstract: A data retention operation is performed in a non-volatile memory in response to detection of a triggering event. The data retention operation includes updating a value of a write parameter of the non-volatile memory and storing into the non-volatile memory at least one copy of contents of a boot portion of the non-volatile memory using the updated value of the write parameter. The updated value of the write parameter increases retention of stored data during extended periods of inactivity at the non-volatile memory.Type: GrantFiled: May 21, 2015Date of Patent: April 10, 2018Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Yacov Duzly, Christopher Scott Moore, Karin Alicia Werder, Elad Baram
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Patent number: 9875053Abstract: A device includes a schedule engine including a mode selection input. The schedule engine has an operating mode based on the mode selection input. The operating mode includes an opportunistic scheduling mode based on the mode selection input having a first value and a pipelined scheduling mode based on the mode selection input having a second value. The device further includes a buffer coupled to the schedule engine.Type: GrantFiled: October 14, 2015Date of Patent: January 23, 2018Assignee: Western Digital Technologies, Inc.Inventors: Marina Frid, Igor Genshaft, Einat Inna Zevulun, Yacov Duzly, Amir Shaharabany
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Publication number: 20170344295Abstract: A system and method is disclosed for fast secure destruction or erasure of data in a non-volatile memory. The method may include identifying a fast erase condition, such as an unauthorized access attempt, and then applying a fast erase process to a predetermined number of blocks of the non-volatile memory. The fast erase process may be implemented by applying an erase voltage for less than a full duration needed to place the blocks in a full erase state, but sufficient to make any data in those blocks unreadable. The system may include a non-volatile memory having a plurality of blocks and a controller configured to sequentially apply the erase voltage to a predetermined portion of the blocks for less than a time needed to fully erase those blocks such that the controller may rapidly make data unreadable without taking the full time to completely erase those blocks.Type: ApplicationFiled: May 31, 2016Publication date: November 30, 2017Applicant: SanDisk Technologies LLCInventors: Liron Sheffi, Yuval Kenan, Amir Shaharabany, Yacov Duzly
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Publication number: 20170293553Abstract: A device includes a memory and a controller coupled to the memory. The controller is configured to maintain a first address translation table associated with the memory and a second address translation table associated with the memory. The controller is further configured to receive a command to erase the memory. The controller is further configured to switch an indicator of an active address translation table from the first address translation table to the second address translation table in response to receiving the command.Type: ApplicationFiled: April 6, 2016Publication date: October 12, 2017Inventors: TAL HELLER, ASAF GARFUNKEL, HADAS OSHINSKY, YACOV DUZLY, AMIR SHAHARABANY, JUDAH GAMLIEL HAHN
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Publication number: 20170168716Abstract: Systems, methods and/or devices are used to pair metablocks in a non-volatile storage device. In one aspect, a method of data organization of a memory device includes, writing data to and reading data from respective metablocks in a set of metablocks. The method further includes while performing said writing and reading: (1) accessing one or more management data structures in controller memory, identifying two or more metablock pairs; (2) accessing and updating metablock status information indicating which metablocks of the set of metablocks are closed, free and open; and (3) accessing and updating a valid count, corresponding to a number of sub-block memory units having valid data for each of a plurality of metablocks in the set of metablocks.Type: ApplicationFiled: November 10, 2016Publication date: June 15, 2017Inventors: Amir Shaharabany, Hadas Oshinsky, Yacov Duzly, James Fitzpatrick
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Patent number: 9658777Abstract: A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided.Type: GrantFiled: April 9, 2014Date of Patent: May 23, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yacov Duzly, Hadas Oshinsky, Shahar Bar-Or, Judah Gamliel Hahn
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Patent number: 9652154Abstract: A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided.Type: GrantFiled: April 9, 2014Date of Patent: May 16, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yacov Duzly, Hadas Oshinsky, Shahar Bar-Or, Judah Gamliel Hahn
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Patent number: 9645741Abstract: A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided.Type: GrantFiled: April 9, 2014Date of Patent: May 9, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yacov Duzly, Hadas Oshinsky, Shahar Bar-Or, Judah Gamliel Hahn
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Patent number: 9645742Abstract: A storage module and host device for storage module defragmentation are disclosed. In one embodiment, a host controller sends a storage module a first set of logical block addresses of a file stored in the storage module. The host controller receives a metric from the storage module indicative of a fragmentation level of the file in physical blocks of memory in the storage module. If the metric is greater than a threshold, the host controller reads the file and then writes it back to the storage module using a different set of logical block addresses. To avoid sending the file back and forth, in another embodiment, the host controller sends the fragmentation threshold and the different set of logical block addresses to the storage module. The storage module then moves the file itself if the metric indicative of the fragmentation level is greater than the threshold. Other embodiments are provided.Type: GrantFiled: April 9, 2014Date of Patent: May 9, 2017Assignee: SANDISK TECHNOLOGIES LLCInventors: Yacov Duzly, Hadas Oshinsky, Shahar Bar-Or, Judah Gamliel Hahn