Abstract: A device includes a first leg including a first connector. The first connector includes multiple electrical contacts. The device includes a second leg substantially parallel to the first leg and configured with a connector, a set of conductors, or both. The device includes a transverse portion connected to the first leg and to the second leg. Together, the transverse portion and the first and second legs form a substantially rigid or semi-rigid body. The transverse portion includes multiple conductors electrically coupling respective connectors on the first and second legs.

Abstract: A mechanism is presented memory circuits, such a NAND-type flash memories, to autonomously protect themselves from temporary and short power drops. A detection mechanism looks for the supply voltage to drop below a function voltage for a period of time. When such an event occurs, a suspend mechanism is activated, and after completing the last micro-operation (such as a program pulse) the memory freezes. When power is again stable at an operational level, the suspended operation is resumed. The memory controller can then be notified upon occurrence of such voltage drop by polling a special status bit. Examples of how the pausing can be implemented include altering of clock signals and suspending sub-phases of larger operations.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: Techniques are presented to operate a greater number of dice in parallel while not exceeding peak current limits. The device can arbitrate between multiple dice and, when needed, suspend operations on one or more dice in a way to average the chance of performance penalty so that all chips will proceed with write at an equal probability. In other aspects, the suspension of operations can be weighted based on factors such as the relative speed of the different dice or differing loads.

Abstract: Circuitry and method for detecting occurrence of a reflow process to an embedded storage device are disclosed. A temperature sensing device includes a resistor, a temperature sensor, and a comparator. The first terminal of the resistor is coupled to a voltage source, and the second terminal of the resistor is coupled to both the first terminal of the temperature sensor and the first input of the comparator. The second terminal of the temperature sensor is grounded and the second input of the comparator is coupled to a reference voltage. The resistance state of the temperature sensor changes from a first resistance state to a second resistance state when the temperature surrounding the temperature sensor reaches a threshold. The comparator generates an output based on the resistance changes of the temperature sensor. The generated output may indicate whether a reflow process has occurred to the embedded storage device.

Abstract: A mechanism is presented memory circuits, such a NAND-type flash memories, to autonomously protect themselves from temporary and short power drops. A detection mechanism looks for the supply voltage to drop below a function voltage for a period of time. When such an event occurs, a suspend mechanism is activated, and after completing the last micro-operation (such as a program pulse) the memory freezes. When power is again stable at an operational level, the suspended operation is resumed. The memory controller can then be notified upon occurrence of such voltage drop by polling a special status bit. Examples of how the pausing can be implemented include altering of clock signals and suspending sub-phases of larger operations.

Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.

Abstract: A bridge includes a host interface via which data/commands are received from and transferred to a host, and a storage device interface via which data/commands are received from and transferred to a storage device. The bridge also includes one SDPC, a controller and a switching system that is configurable by the controller to connect the protocol converter to the host interface and the storage device interface if the storage device protocol used by the host device differs from the storage device protocol used by the storage device, and to connect the host device interface to the storage device interface, not via the bi-directional protocol converter, if the two storage device protocols are the same. The bridge may include two SDPCs, each for converting a different protocol to the host protocol and vice versa, with the switching system being configurable to switch between the two SDPCs.

Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.

Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.

Abstract: A storage device with a memory, a controller, a storage device interface and a host interface, and a method of data transfer to and from a storage device are provided. The storage device is operative to connect with a host device and the storage device interface is operative to couple with an add-on memory. When the host interface is connected to a host device, the controller is configured to receive a data transfer command specifying a memory address from the host interface; and if the memory address is beyond the address space of the memory, to route the data transfer command to the storage device interface for access to the add-on memory. The address space of the memory and an address space of the add-on memory are addressed as one integral address space transparently to the host.

Abstract: Systems and methods of memory management storage to a host device are disclosed. A method is performed in a data storage device with a non-volatile memory and a controller operative to manage the non-volatile memory and to generate management data for managing the non-volatile memory. The method includes performing, at a given time, originating at the controller data management transfer to a host device or originating at the controller data management retrieval from the host device.

Abstract: The present invention discloses methods for improving data-retrieval times from a non-volatile storage device. A method for preloading data to improve data-retrieval times from a non-volatile storage device, the method including the steps of: providing a cache memory for preloading the data upon a host-system request to read the data; determining that a plurality of data segments that constitute a non-contiguous data object, stored in the storage device such that at least one data segment is non-contiguous to a preceding data segment in the data object, are in a predictable sequence; and preloading a non-contiguous next data segment in the predictable sequence into the cache memory after loading a current data segment into a host system from the cache memory, wherein the next data segment is preloaded prior to the host-system request to read the next data segment.

Abstract: A bridge includes a host interface via which data/commands are received from and transferred to a host, and a storage device interface via which data/commands are received from and transferred to a storage device. The bridge also includes one SDPC, a controller and a switching system that is configurable by the controller to connect the protocol converter to the host interface and the storage device interface if the storage device protocol used by the host device differs from the storage device protocol used by the storage device, and to connect the host device interface to the storage device interface, not via the bi-directional protocol converter, if the two storage device protocols are the same. The bridge may include two SDPCs, each for converting a different protocol to the host protocol and vice versa, with the switching system being configurable to switch between the two SDPCs.

Abstract: A method and system are disclosed that permit a storage device to remain fully functional despite running out of a sufficient supply of spare blocks in memory. The storage device includes a non-volatile memory and a controller, where the controller is configured to detect an insufficiency of spare blocks and convert operative blocks to spare blocks. The method includes techniques for selecting certain operative blocks for conversion to spare blocks using the storage manager on the storage device and a file system manager that may or may not be part of the storage device.

Abstract: A method and system for enhancing efficiency in power failure handling in flash memory devices is disclosed. The method includes the controller of a storage device receiving a page of data, selecting a block having a desired back-up cost and copying previously stored data in the selected block to a back-up block prior to writing the received page to the selected block based on a category of the previously stored data. The system includes non-volatile memory having a plurality of operative blocks, at least one spare block and a controller. The controller is configured to receive a page of data, select an operative block in the memory having a desired back-up cost, and copy previously stored data in the selected block to a spare block based on a category of the previously stored data prior to writing the received page to the selected block.

Abstract: Protection against computer viruses is provided by a storage device having a memory, a controller, and a content scanning module used for scanning files for viruses. Infected files are indicated to a virus handling module that resides external to the storage device. The virus handling module may alter access to the infected files and/or indicate their presence to other system components. Such virus scanning mechanism can be built within the controller of the storage device. The protection against computer viruses may be provided by a method that includes transferring file data from the memory to the controller, reconstructing the files from the file data, activating the controller to check the reconstructed files for viruses, and indicating the infected files to the virus handling module. By using the controller within the storage device to scan for viruses, the burden on the host can be greatly reduced.

Abstract: The present invention discloses methods for improving data-retrieval times from a non-volatile storage device. A method for preloading data to improve data-retrieval times from a non-volatile storage device, the method including the steps of: providing a cache memory for preloading the data upon a host-system request to read the data; determining that a plurality of data segments that constitute a non-contiguous data object, stored in the storage device such that at least one data segment is non-contiguous to a preceding data segment in the data object, are in a predictable sequence; and preloading a non-contiguous next data segment in the predictable sequence into the cache memory after loading a current data segment into a host system from the cache memory, wherein the next data segment is preloaded prior to the host-system request to read the next data segment.

Abstract: The present invention discloses devices for improving data-retrieval times from a non-volatile storage device. A non-volatile storage device including: a storage memory for storing data; a cache memory for preloading the data upon a host-system request to read the data; and a storage-device controller configured: to determine that a plurality of data segments that constitute a non-contiguous data object, stored in the storage memory such that at least one data segment is non-contiguous to a preceding data segment in the data object, are in a predictable sequence; and to preload a non-contiguous next data segment in the predictable sequence into the cache memory after loading a current data segment into a host system from the cache memory, wherein the next data segment is preloaded prior to the host-system request to read the next data segment.