Abstract: Methods, systems, and computer program products for container image management are disclosed. In a method, a first group of operations that are performed in respective layers in a base image are obtained. A second group of operations that are performed in respective layers not comprised in the base image are obtained. The second group of operations are optimized based on a comparison between the first and second groups of operations. A destination container image is generated based on the optimized second group of operations and the base image.

Abstract: A data-compression analyzer can rapidly make a binary decision to compress or not compress an input data block or can use a slower neural network to predict the block's compression ratio with a regression model. A Concentration Value (CV) that is the sum of the squares of the frequencies and a Number of Zero (NZ) symbols are calculated from an un-sorted symbol frequency table. A rapid decision to compress is signaled when their product CV*NZ exceeds a horizontal threshold THH. During training, CV*NZ is plotted as a function of compression ratio C % for many training data blocks. Different test values of THH are applied to the plot to determine true and false positive rates that are plotted as a Receiver Operating Characteristic (ROC) curve. The point on the ROC curve having the largest Youden index is selected as the optimum THH for use in future binary decisions.

Abstract: The disclosure provides a battery pack, a battery thermal management system and a battery thermal management control method. The battery pack includes: a housing, a bracket and a battery cell. The housing is provided with an accommodation space. The bracket is arranged in the accommodation space, which forms at least one accommodation cavity with the accommodation space. The battery cell is arranged in the accommodation cavity, and at least one heat dissipation passage is opened in the accommodation cavity. At least one fan is arranged on one side of the heat dissipation passage to suck or blow air to the heat dissipation passage. Compared with the prior art, the battery pack of the disclosure has an active heat dissipation function while satisfying waterproofing.

Abstract: A charging device and an application thereof are provided. The charging device includes a housing, defining a receiving cavity; a circuit board, arranged in the receiving cavity; an input part, provided on the housing and configured for connection to an external power supply; and a plurality of output parts, provided on the housing, the input part and the output part being electrically connected via the circuit board. Each of the output parts includes at least one terminal, and the terminal is arranged in the receiving cavity and passes through the housing to a surface of the housing. The charging device can be applied to charge a wide range of electronic devices.

Abstract: The disclosure provides a battery pack, a power tool system and a charging system. The battery pack includes a battery pack housing in which a battery cell assembly and a circuit board are mounted. The circuit board is electrically connected with the battery cell assembly. A plurality of Type-C connectors are arranged on the circuit board and electrically connected to the circuit board to realize an electrical connection between the battery cell assembly and the Type-C connectors, and are configured to connect external devices.

Abstract: A data-compression analyzer can rapidly make a binary decision to compress or not compress an input data block or can use a slower neural network to predict the block's compression ratio with a regression model. A Concentration Value (CV) that is the sum of the squares of the frequencies and a Number of Zero (NZ) symbols are calculated from an un-sorted symbol frequency table. A rapid decision to compress is signaled when their product CV*NZ exceeds a horizontal threshold THH. During training, CV*NZ is plotted as a function of compression ratio C % for many training data blocks. Different test values of THH are applied to the plot to determine true and false positive rates that are plotted as a Receiver Operating Characteristic (ROC) curve. The point on the ROC curve having the largest Youden index is selected as the optimum THH for use in future binary decisions.

Abstract: A train-linking lossless data compressor examines a block of data and uses a same coder to generate a same code when all data values in the input block are identical. When the input data is not all the same value, then a Gaussian coder, a Laplace coder, and a delta coder are activated in parallel. The three compressed code lengths are compared and the smallest code length is output as the compressed code when it is smaller than a copy code length. The copy code is a tag followed by copying all the data in the input block. When the smallest of the three compressed code lengths is larger than the copy code length, the file is not compressible, and the copy code is output. No frequency table is required so latency is low. The delta coder subtracts data values from an average value of the last data block.

Abstract: This present application provides a semiconductor packaging method and a semiconductor packaging structure. The semiconductor packaging method includes: forming an encapsulating structure, the encapsulating structure including an encapsulation layer and a chip, the chip provided on a front side thereof with a plurality of bonding pads, the encapsulation layer covering at least side faces of the chip; forming a rewiring layer on the side of the encapsulating structure close to the front side of the chip, the rewiring layer configured for external connection of the bonding pads on the chip; forming a dielectric layer, the dielectric layer covering the rewiring layer, the dielectric layer provided therein with a through hole in which the rewiring layer is exposed; and forming a pin layer on the side of the dielectric layer away from the chip, the pin layer electrically connected to the rewiring layer through the through hole.

Abstract: A neural network receives mono-color pixels in a Bayer pattern from an image sensor and interpolates pixels to generate full-color RGB pixels while also enlightening the image for better detail. A Back-Projection (BP) layer is added to each contracting layer in a U-net convolution neural network where feature depth is increased as pixels are downsampled, while a BP channel shrink layer is added to each expansion layer where feature depth is reduced to upsample and increase pixel resolution. Convolution layers in the BP layer lighten and darken images to generate an error that is then lightened and added to a weighted lightened input. The neural network learns the best weightings to correct for noise and error in the lightening process in these BP layers. Noise is reduced further by repeating a convolution and leaky Rectified Linear Unit (lrelu) in series for the first convolution in the BP layer that performs lightening.

Abstract: A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.

Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Abstract: A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.

Abstract: A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

Abstract: A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.

Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Abstract: An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.

Abstract: A small and ultra-thin power semiconductor device and a preparation method are disclosed. The device includes a chip mounting unit with a plurality of pads with a plate arranged on top surface of each pad; a semiconductor chip flipped and attached on the chip mounting unit, where the electrodes at the front of the chip are electrically connected to the pads; a plastic packaging body covering the chip mounting units and the chip, where the top surface of the plate and the back surface of the chip are exposed out from top surface of the plastic packaging body and the bottom surfaces of the pads are exposed out of the bottom surface of the plastic packaging body; a plurality of top metal segments arranged on the top surface of the plastic packaging body and electrically connected to the top surface of each plate and the back surface of the chip.

Abstract: An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.

Abstract: A semiconductor package includes a lead frame having a die paddle and a plurality of leads connected to die paddle, where each lead has a lead surface parallel to die paddle and is a continuous extension bending upward from die paddle. A semiconductor chip is mounted on die paddle, where drain metal layer covering a first surface of chip is connected to die paddle, and source metal layer and gate metal layer are located on a second surface opposite to first surface with gate metal layer located at one corner of the second surface. A source metal plate and a gate metal plate are attached on source metal layer and gate metal layer respectively. A molding layer covers lead frame, semiconductor chip, source metal plate and gate metal plate, where lead surface, top surfaces of source metal plate and gate metal plate are exposed from top surface of molding layer.