Abstract: A power semiconductor package with a small footprint and a preparation method thereof are disclosed. The first semiconductor chip and second semiconductor chip are attached on the front and back sides of a die paddle. Conductive pads are then attached on the electrodes at the top surfaces of the first and second semiconductor chips flowed by the formation of a plastic package body covering the die paddle, first and second semiconductor chips, the conductive pads, where a side surface of a conductive pad is exposed from a side surface of the plastic package body.

Abstract: A small and ultra-thin power semiconductor device and a preparation method are disclosed. The device includes a chip mounting unit with a plurality of pads with a plate arranged on top surface of each pad; a semiconductor chip flipped and attached on the chip mounting unit, where the electrodes at the front of the chip are electrically connected to the pads; a plastic packaging body covering the chip mounting units and the chip, where the top surface of the plate and the back surface of the chip are exposed out from top surface of the plastic packaging body and the bottom surfaces of the pads are exposed out of the bottom surface of the plastic packaging body; a plurality of top metal segments arranged on the top surface of the plastic packaging body and electrically connected to the top surface of each plate and the back surface of the chip.

Abstract: A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

Abstract: A small and ultra-thin power semiconductor device and a preparation method are disclosed. The device includes a chip mounting unit with a plurality of pads with a plate arranged on top surface of each pad; a semiconductor chip flipped and attached on the chip mounting unit, where the electrodes at the front of the chip are electrically connected to the pads; a plastic packaging body covering the chip mounting units and the chip, where the top surface of the plate and the back surface of the chip are exposed out from top surface of the plastic packaging body and the bottom surfaces of the pads are exposed out of the bottom surface of the plastic packaging body; a plurality of top metal segments arranged on the top surface of the plastic packaging body and electrically connected to the top surface of each plate and the back surface of the chip.

Abstract: A preparation method of small and ultra-thin power semiconductor device comprising the steps of: providing a chip mounting unit with a plurality of pads with a plate arranged on top surface of each pad; flipping and attaching a semiconductor chip on the chip mounting unit, where the electrodes at the front of the chip are electrically connected to the pads; forming a plastic packaging body covering the chip mounting units and the chip, where the top surface of the plate and the back surface of the chip are exposed out from top surface of the plastic packaging body and the bottom surfaces of the pads are exposed out of the bottom surface of the plastic packaging body; forming a plurality of top metal segments arranged on the top surface of the plastic packaging body and electrically connected to the top surface of each plate and the back surface of the chip.

Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Abstract: A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

Abstract: This invention discloses a method for object tracking, including determination of an area scaling ratio of the object in a video image sequence. In one embodiment, a centroid of the object is determined. One or more directed straight lines are selected, each passing through the centroid, extending from an end of the object's boundary to an opposite end thereof, and having a direction that is upward. A length scaling ratio for each directed straight line is determined by: determining a motion vector for each selected pixel on the line; computing a scalar component of the motion vector projected onto the line; estimating a change of the line's length according to the scalar components obtained for all pixels; and determining the length scaling ratio according to the change of the line's length. The area scaling ratio is computed based on the length scaling ratios for all directed straight lines.

Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Abstract: A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

Abstract: A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.

Abstract: This invention discloses a method for determining an area scaling ratio of an object in a video image sequence. In one embodiment, a centroid of the object is determined. One or more directed straight lines are selected, each passing through the centroid, extending from an end of the object's boundary to an opposite end thereof, and having a direction that is upward. A length scaling ratio for each directed straight line is determined by: determining a motion vector for each selected pixel on the line; computing a scalar component of the motion vector projected onto the line; estimating a change of the line's length according to the scalar components obtained for all pixels; and determining the length scaling ratio according to the change of the line's length. The area scaling ratio is computed based on the length scaling ratios for all directed straight lines.

Abstract: A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.

Abstract: Method and apparatus for providing a fast and accurate video coding process are disclosed. After checking the coding history of certain coded video frame units of a video, the order of the inter prediction and the intra prediction is adaptively exchanged for each coding video frame unit of an inter frame. Furthermore, the computations for coding modes in the latter part of the computation order are selectively skipped so as to speed up the coding process without degrading the video quality.

Abstract: This invention relates to method and apparatus for subpixel-based down-sampling. This invention implements an adaptive filter 140 based on edge detection, which removes visible color fringing artifacts while efficiently retaining sharpness.

Abstract: The present invention relates to method and apparatus for improving video quality. The present invention provides a unified loop filter including: a pixel determining unit which determines the type of a pixel based on boundary strength; a similarity transforming unit which transforms a nonlinear filter into a nonlinear similarity-ordered statistics filter; and an integrating unit which integrates the nonlinear similarity-ordered statistics filter with a linear image filtering portion. The unified loop filter is applicable to filter reconstructed frames when an encoder or a decoder is processing a video signal.

Abstract: The invention is used in video coding. Systems, apparatuses and methods for processing an order-16 integer transform from an order-8 transform are provided. The order-16 transform method involves expanding an order-8 transform by generating an order-16 integer matrix and a scaling matrix.

Abstract: The presently claimed invention adaptively selects a local de-interlacing method according to information from a compressed video bitstream. According to one embodiment, successive images from a video bitstream are first reconstructed. Syntax elements, selected from a macroblock type, a macroblock partition, a motion vector, a distance from a reference frame, the existence of non-zero transform coefficients and the distribution of transform coefficients, are then extracted from this bitstream. Based on the syntax elements, a de-interlacing algorithm is decided from an algorithm set for each image region in a video frame. Algorithms in the algorithm set include motion compensation, edge-based line averaging, and line averaging. Each image region is thereby interpolated using the de-interlacing algorithm and complementary motion compensation. The complementary motion compensation de-interlaces the image region using an inverse of motion vectors extracted from a bitstream clip representing neighboring frames.

Abstract: The invention relates to an aqueous cleaning composition for wafers with copper wires that have been treated by chemical mechanical planarization in an integrated circuit processing, comprising 0.1 to 15 wt % of a nitrogen-containing heterocyclic organic base, 0.1 to 35 wt % of an alcohol amine and water. Upon contact with copper-containing semiconductor wafers that have been treated by chemical mechanical planarization for an effective period of time, the aqueous cleaning composition can effectively remove residual contaminants from the surfaces of the wafers, and simultaneously provide the copper-containing semiconductor wafers with a better surface roughness.