Patents by Inventor Yan Xun Xue

Yan Xun Xue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PREPARATION METHOD OF A THIN POWER DEVICE
    Publication number: 20150189764
    Abstract: A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads.
    Type: Application
    Filed: March 13, 2015
    Publication date: July 2, 2015
    Inventors: Yuping Gong, Yan Xun Xue, Ming-Chen Lu, Ping Huang, Jun Lu, Hamza Yilmaz
  • METHOD AND STRUCTURE FOR WAFER LEVEL PACKAGING WITH LARGE CONTACT AREA
    Publication number: 20150162257
    Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.
    Type: Application
    Filed: December 5, 2013
    Publication date: June 11, 2015
    Inventor: Yan Xun Xue
  • Hybrid packaged lead frame based multi-chip semiconductor device with multiple semiconductor chips and multiple interconnecting structures
    Patent number: 9054091
    Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: June 9, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Peter Wilson, Yan Huo, Zhiqiang Niu, Ming-Chen Lu
  • Semiconductor packaging method using connecting plate for internal connection
    Patent number: 9040357
    Abstract: A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: May 26, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Jun Lu, Kai Liu, Yan Xun Xue
  • Thin power device and preparation method thereof
    Patent number: 9006901
    Abstract: A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: April 14, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yuping Gong, Yan Xun Xue, Ming-Chen Lu, Ping Huang, Jun Lu, Hamza Yilmaz
  • METHOD FOR PACKAGING A POWER DEVICE WITH BOTTOM SOURCE ELECTRODE
    Publication number: 20150087114
    Abstract: A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.
    Type: Application
    Filed: September 20, 2013
    Publication date: March 26, 2015
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Jun Lu, Lei Shi, Liang Zhao, Ping Huang
  • Packaged power semiconductor with interconnection of dies and metal clips on lead frame
    Patent number: 8981539
    Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 17, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Hamza Yilmaz
  • Multi-Die Power Semiconductor Device Packaged On a Lead Frame Unit with Multiple Carrier Pins and a Metal Clip
    Publication number: 20150069590
    Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.
    Type: Application
    Filed: November 20, 2014
    Publication date: March 12, 2015
    Inventors: Yan Xun Xue, Hamza Yilmaz
  • Stacked multi-chip bottom source semiconductor device and preparation method thereof
    Patent number: 8952509
    Abstract: The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: February 10, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Hamza Yilmaz, Yueh-Se Ho, Yan Xun Xue, Jun Lu, Xiaotian Zhang, Zhi Qiang Niu, Ming-Chen Lu, Liang Zhao, YuPing Gong, GuoFeng Lian
  • PACKAGING STRUCTURE OF A SEMICONDUCTOR DEVICE
    Publication number: 20150021753
    Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.
    Type: Application
    Filed: September 17, 2014
    Publication date: January 22, 2015
    Inventors: Yueh-Se Ho, Yan Xun Xue, Jun Lu, Lei Shi, Liang Zhao, Ping Huang
  • THIN POWER DEVICE AND PREPARATION METHOD THEREOF
    Publication number: 20150021780
    Abstract: A thin power device comprises a substrate having a first set of first contact pads at a front surface of the substrate electrically connecting to a second set of second contact pads at a back surface of the substrate, a through opening opened from the front surface and through the substrate exposing a third contact pad at the back surface of the substrate, a semiconductor chip embedded into the through opening with a back metal layer at a back surface of the semiconductor chip attached on the third contact pad, and a plurality of conductive structures electrically connecting electrodes at a front surface of the semiconductor chip with the corresponding first contact pads in the first sets of first contact pads.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Inventors: Yuping Gong, Yan Xun Xue, Ming-Chen Lu, Ping Huang, Jun Lu, Hamza Yilmaz
  • Double-side exposed semiconductor device
    Patent number: 8933545
    Abstract: A double-side exposed semiconductor device includes an electric conductive first lead frame attached on top of a thermal conductive but electrical nonconductive second lead frame and a semiconductor chip flipped and attached on top of the first lead frame. The gate and source electrodes on top of the flipped chip form electrical connections with gate and source pins of the first lead frame respectively. The flipped chip and center portions of the first and second lead frames are then encapsulated with a molding compound, such that the heat sink formed at the center of the second lead frame and the drain electrode at bottom of the semiconductor chip are exposed on two opposite sides of the semiconductor device. Thus, heat dissipation performance of the semiconductor device is effectively improved without increasing the size of the semiconductor device.
    Type: Grant
    Filed: April 18, 2013
    Date of Patent: January 13, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yuping Gong, Yan Xun Xue
  • Stacked power semiconductor device using dual lead frame
    Patent number: 8933518
    Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: January 13, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Yueh-Se Ho, Lei Shi, Jun Lu, Liang Zhao
  • Structure of mixed semiconductor encapsulation structure with multiple chips and capacitors
    Patent number: 8933550
    Abstract: A semiconductor package for power converter application comprises a low-side MOSFET chip and a high-side MOSFET chip stacking one over the other. The semiconductor package may further enclose a capacitor whereas the capacitor may be a discrete component or an integrated component on chip level with the low-side MOSFET. The semiconductor package may further comprise a PIC chip to provide a complete power converter on semiconductor chip assembly package level.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: January 13, 2015
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Yan Xun Xue, Anup Bhalla, Jun Lu
  • WAFER LEVEL CHIP SCALE PACKAGE WITH EXPOSED THICK BOTTOM METAL
    Publication number: 20150001686
    Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.
    Type: Application
    Filed: September 8, 2014
    Publication date: January 1, 2015
    Inventor: Yan Xun Xue
  • POWER CONTROL DEVICE AND PREPARATION METHOD THEREOF
    Publication number: 20140361419
    Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Yan Xun Xue, Hamza Yilmaz
  • HYBRID PACKAGING MULTI-CHIP SEMICONDUCTOR DEVICE AND PREPARATION METHOD THEREOF
    Publication number: 20140361420
    Abstract: A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.
    Type: Application
    Filed: June 10, 2013
    Publication date: December 11, 2014
    Inventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu, Peter Wilson, Yan Huo, Zhiqiang Niu, Ming-Chen Lu
  • A SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET
    Publication number: 20140361418
    Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.
    Type: Application
    Filed: June 7, 2013
    Publication date: December 11, 2014
    Inventors: Yan Xun Xue, Yueh-Se Ho, Hamza Yilmaz, Jun Lu
  • Wafer level chip scale package
    Patent number: 8890296
    Abstract: A semiconductor device, a method of manufacturing semiconductor devices and a circuit package assembly are described. A semiconductor device can have a semiconductor substrate with first and second surfaces and a sidewall between them. First and second conductive pads on the first and second surfaces are in electrical contact with corresponding first and second semiconductor device structures in the substrate. An insulator layer on the first surface and sidewall covers a portion of the first conductive pad on the first surface. An electrically conductive layer on part of the insulator layer on the first conductive pad and sidewall is in electrical contact with the second conductive pad. The insulator layer prevents the conductive layer from making electrical contact between the first and second conductive pads.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 18, 2014
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yueh-Se Ho, Yan Xun Xue
  • Flip-chip semiconductor chip packing method
    Patent number: 8877555
    Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.
    Type: Grant
    Filed: November 16, 2012
    Date of Patent: November 4, 2014
    Assignee: Alpha & Omega Semiconductor, Inc.
    Inventors: Lei Shi, Yan Xun Xue, Yuping Gong