Abstract: A bottom source power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a gate electrode and a source electrode formed on an initial insulation layer on a first surface of a semiconductor chip and a drain electrode formed on a second surface of the semiconductor chip. The source electrode includes a source metal, a source electrode bump formed on the source metal and a source electrode metal layer on top of the source electrode bump. A first insulation layer covers the gate electrode. A through via aligned to the gate electrode is formed from the second surface of the chip to expose a portion of the gate electrode from the second surface.

Abstract: A wafer process for MCSP comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer covering metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal seed layer and a thick metal layer at bottom surface of wafer in recessed space in a sequence; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and the metal seed and metal layers along the scribe line.

Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

Abstract: A method for forming a wafer level chip scale (WLCS) package device with a thick bottom metal comprising the step of attaching a lead frame comprising a plurality of thick bottom metals onto a back metal layer of a semiconductor wafer including a plurality of semiconductor chips having a plurality of bonding pads formed on a front surface of each chip, each thick bottom metal is aligned to a central portion of each chip; a plurality of back side cutting grooves are formed along the scribe lines and filled with a package material, the package material are cut through thus forming a plurality of singulated WLCS package devices.

Abstract: A semiconductor package method for co-packaging high-side (HS) and low-side (LS) semiconductor chips is disclosed. The HS and LS semiconductor chips are attached to two opposite sides of a lead frame, with a bottom drain electrode of the LS chip connected to a top side of the lead frame and a top source electrode of the HS chip connected to a bottom side of the lead frame through a solder ball. The stacking configuration of HS chip, lead frame and LS chip reduces the package size. A bottom metal layer covering the bottom of HS chip exposed outside of the package body provides both electrical connection and thermal conduction.

Abstract: A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

Abstract: A method of making a semiconductor packaged device comprises mounting onto a lead frame a bottom of a molded semiconductor chip having a first plastic package body covering a top face of a semiconductor chip, encapsulating the lead frame and the semiconductor chip with a second plastic package body with top surfaces of conductive contact bodies electrically connected to electrodes on the top surface of the semiconductor chip exposed and plating conductive pads on a top surface of the assembly structure to provide external electrical connections to the electrodes through the conductive contact bodies.

Abstract: A method for preparing semiconductor devices in a flip chip process comprises forming deep grooves surrounding each of the semiconductor chips; depositing a first plastic package material to form a first plastic package layer covering front surface of the semiconductor wafer and filling the deep grooves; depositing a metal layer at back surface of the semiconductor wafer after grinding; grinding an outermost portion of the metal layer thus forming a ring area located at back surface around edge of the semiconductor wafer not covered by the metal layer; cutting the first plastic package layer, the semiconductor wafer, the metal layer and the first plastic package material filled in the deep grooves along a straight line formed by two ends of each of the deep grooves filled with the first plastic package material; and picking up the semiconductor devices and mounting on a substrate without flipping the semiconductor devices.

Abstract: A packaging method with backside wafer dicing includes the steps of forming a support structure at the front surface of the wafer then depositing a metal layer on a center area of the backside of the wafer after grinding the wafer backside to reduce the wafer thickness; detecting from the backside of the wafer sections of scribe lines formed in the front surface in the region between the edge of the metal layer and the edge of the wafer and cutting the wafer and the metal layer from the wafer backside along a straight line formed by extending a scribe line section detected from the wafer backside.

Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

Abstract: A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

Abstract: Preparation methods of forming packaged semiconductor device, specifically for flip-chip vertical power device, are disclosed. In these methods, a vertical semiconductor chip is flip-chip attached to a lead frame and then encapsulated with plastic packing materials. Encapsulated chip is then thinned to a predetermined thickness. Contact terminals connecting the chip with external circuit are formed by etching at least a bottom portion of the lead frame connected.

Abstract: A semiconductor encapsulation comprises a lead frame further comprising a chip carrier and a plurality of pins in adjacent to the chip carrier. A plurality of grooves opened from an upper surface of the chip carrier partially dividing the chip carrier into a plurality of chip mounting areas. A bottom portion of the grooves is removed for completely isolate each chip mounting area, wherein a width of the bottom portion of the grooves removed is smaller than a width of the grooves. In one embodiment, a groove is located between the chip carrier and the pins with a bottom portion of the groove removed for isolate the pins from the chip carrier, wherein a width of the bottom of the grooves removed is smaller than a width of the grooves.

Abstract: A die attach method for a semiconductor chip with a back metal layer located at the back surface of the semiconductor chip comprises the steps of forming a bonding ball array including a plurality of bonding balls with a same height on a die attach area at a top surface of a die paddle; depositing a die attach material in the bonding ball array area with a thickness of the die attach material equal or slightly larger than the height of the bonding ball; attaching the semiconductor chip to the die attach area at the top surface of the die paddle by the die attach material, wherein the bonding ball array controls the bond line thickness of the die attach material between the back metal layer and the top surface of the die paddle and prevents the semiconductor chip from rotating on the die attach material when it is melted.

Abstract: A semiconductor package with connecting plate for internal connection comprise: a plurality of chips each having a plurality of contact areas on a top surface; one or more connecting plates having a plurality of electrically isolated connecting plate portions each connecting a contact area of the semiconductor chips. The method of making the semiconductor package includes the steps of connecting one or more connecting plates to a plurality of semiconductor chips, applying a molding material to encapsulate the chips and the connecting plates, separating a plurality of connecting plate portions of the connecting plates by shallow cutting through or by grinding.

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.

Abstract: The invention relates to a power semiconductor device and a preparation method, particularly relates to preparation of stacked dual-chip packaging structure of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) using flip chip technology with two interconnecting plates. The first chip is flipped and attached on the base such that the first chip is overlapped with the third pin; the back metal layer of the first chip is connected to the bonding strip of the first pin through a first interconnecting plate; the second chip is flipped and attached on a main plate portion of the first interconnecting plate such that the second chip is overlapped with the fourth pin; and the back metal layer of the second chip is connected to the bonding strip of the second pin through the second interconnecting plate.

Abstract: A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface, grinding the wafer back surface and etch through holes, depositing a metal to fill the through holes and covering wafer backside, cutting through the wafer from wafer backside forming a plurality of grooves separating each chip then depositing a second packaging layer filling the grooves and covering the wafer back metal, reducing the first packaging layer thickness to expose the second packaging layer filling the grooves and forming a plurality of contact pads overlaying the first packaging layer thereafter cutting through the second packaging layer in the grooves to form individual package.

Abstract: A semiconductor package is provided with an Aluminum alloy lead-frame without noble metal plated on the Aluminum base lead-frame. Aluminum alloy material with proper alloy composition and ratio for making an aluminum alloy lead-frame is provided. The aluminum alloy lead-frame is electroplated with a first metal electroplating layer, a second electroplating layer and a third electroplating layer in a sequence. The lead-frame electroplated with the first, second and third metal electroplating layers is then used in the fabrication process of a power semiconductor package including chip connecting, wire bonding, and plastic molding. After the molding process, the area of the lead-frame not covered by the molding compound is electroplated with a fourth metal electroplating layer that is not easy to be oxidized when exposing to air.

Abstract: A semiconductor device comprises an aluminum alloy lead-frame with a passivation layer covering an exposed portion of the aluminum alloy lead-frame. Since aluminum alloy is a low-cost material, and its hardness and flexibility are suitable for deformation process, such as punching, bending, molding and the like, aluminum alloy lead frame is suitable for mass production; furthermore, since its weight is much lower than copper or iron-nickel material, aluminum alloy lead frame is very convenient for the production of semiconductor devices.