Abstract: The disclosure facilitates fingerprint recognition, user authentication, and prevention of loss of control of personal information and identity theft. The disclosure also facilitates identifying spoofed fingerprint authentication attempts, and/or securing user touch sensitive devices against spoofed fingerprint authentication attempts.

Abstract: Techniques that can improve efficiency of a touch sensitive device are presented. A touch controller (TC) can comprise a hover classification engine and an application processor (AP) can comprise a touch classification engine usable to classify touch or hover interactions of an object(s) with a touch sensitive surface (TSS) of the device. In response to classifying a touch or hover interaction with TSS as unintentional, AP can reject such interaction and can transition from an active state to an inactive state. TC can continue to monitor touch or hover interactions with TSS. In response to determining there is an intentional touch interaction with TS S or no unintentional face/ear interaction with TSS, TC can transmit a notification signal to AP. In response to the notification signal, AP can transition from the inactive state to active state, and can process the intentional touch interaction or monitor the TSS.

Abstract: The invention relates to an in-utero ventriculoamniotic shunting device that includes a shunt tube (26) composed of polymer composite and having metallic wire embedded therein, one or more anchors (30) composed of superelastic wire, e.g., thermal shape-set nitinol structures, that are mechanically attached to an exterior surface of the shunt tube (26), and a one-way passive valve (32) composed of a thin polymer membrane. The anchors (30) are effective to prevent migration and dislodgement of the shunting device following its deployment, and the valve (32) is effective to prevent the backflow of amniotic fluid (23).

Abstract: A neck-hanging massaging device includes an elastic arm, a first handle, a second handle, an electrode assembly and an electric pulse generating device. The first handle and the second handle are fixedly connected to the two sides of the elastic arm. The electrode assembly is arranged on the elastic arm. The electric pulse generating device is electrically connected with the electrode assembly. The electric pulse generating device is arranged in the first handle.

Abstract: A reset sub-circuit can sample the reset signal based on a low-speed clock reference signal to generate a series of sampled reset signals. A phase relation between a first selected one of the series of sampled reset signals and the high-speed clock signal at the clock input of each sampler can be measured to generate reset trigger signals corresponding to each of a plurality of samplers. A second selected one of the series of sampled reset signals can be sampled based on the high-speed clock signal to generate a positive sampled reset signal and a negative sampled reset signal. The reset sub-circuit can select between the positive sampled reset signal and the negative sampled reset signal based on the reset trigger signals corresponding to each sampler to generate the synchronous reset signal.

Abstract: A sampling circuitry with a temperature insensitive bandwidth can include a temperature dependent current source, a source-follower amplifier, a storage element and a clocked transmission gate. The source-follower amplifier can be biased by the temperature dependent current source. The source-follower amplifier can be coupled to an input signal node, and the clocked transmission gate can be coupled to a clock signal. The clocked transmission gate can be coupled between an output of the source-follower amplifier and a combination of the storage element and an output signal node. A temperature-based variance in an output impedance of source-follower amplifier, an on-resistance of the clocked transmission gate and the capacitance of the storage element can be substantially cancelled by the temperature dependent current source.

Abstract: A reset sub-circuit can sample the reset signal based on a low-speed clock reference signal to generate a series of sampled reset signals. A phase relation between a first selected one of the series of sampled reset signals and the high-speed clock signal at the clock input of each sampler can be measured to generate reset trigger signals corresponding to each of a plurality of samplers. A second selected one of the series of sampled reset signals can be sampled based on the high-speed clock signal to generate a positive sampled reset signal and a negative sampled reset signal. The reset sub-circuit can select between the positive sampled reset signal and the negative sampled reset signal based on the reset trigger signals corresponding to each sampler to generate the synchronous reset signal.

Abstract: The invention relates to endovascular medical implant devices, systems and methods that including a sensing device and a flow diverter device, which are effective to monitor intra-/post-operative hemodynamic properties in the location of a cerebral aneurysm and, hemodynamic alterations following placement of the system for treating ischemic diseases in carotid, coronary and peripheral arteries. The sensing device includes wireless, non-thrombogenic, highly stretchable, ultra-low profile flow sensors.

Abstract: The invention relates to an in-utero ventriculoamniotic shunting device that includes a shunt tube (26) composed of polymer composite and having metallic wire embedded therein, one or more anchors (30) composed of superelastic wire, e.g., thermal shape-set nitinol structures, that are mechanically attached to an exterior surface of the shunt tube (26), and a one-way passive valve (32) composed of a thin polymer membrane. The anchors (30) are effective to prevent migration and dislodgement of the shunting device following its deployment, and the valve (32) is effective to prevent the backflow of amniotic fluid (23).

Abstract: A Boltzmann machine circuit includes: a plurality of circuits each circuit configured to add one or more first values based on one or more outputs of one or more circuits which are included in the plurality of circuits and are other than the circuit and convert an addition result into an analog signal, compare the analog signal with a second value, and output a comparison result; a plurality of arithmetic circuits configured to multiply the respective comparison results by respective weight values and generate the first values; and a control circuit configured to amplify an amplitude of the analog signal generated by each of the plurality of circuits.

Abstract: A Boltzmann machine circuit includes: a plurality of circuits each circuit configured to add one or more first values based on one or more outputs of one or more circuits which are included in the plurality of circuits and are other than the circuit and convert an addition result into an analog signal, compare the analog signal with a second value, and output a comparison result; a plurality of arithmetic circuits configured to multiply the respective comparison results by respective weight values and generate the first values; and a control circuit configured to amplify an amplitude of the analog signal generated by each of the plurality of circuits.

Abstract: A comparator includes an input-stage circuit that sets, in a first operating state, two voltage signals in a first voltage state, and changes, in a second operating state, the two voltage signals from the first voltage state to a second voltage state at different speeds, a latch-stage circuit that includes two field effect transistors and two inverters, the two field effect transistors receiving the two voltage signals at control nodes and disposed between two output nodes and a predetermined potential, the two inverters cross-coupled between the two output nodes and placed in an inactive state in the first operating state and in an active state in the second operating state, and a control circuit that controls current capacities in two paths through which drive voltages are applied to the two inverters, causing the current capacities to be different during at least part of a period of the second operating state.

Abstract: A method for detecting a hysteresis characteristic of a comparator, include: causing a controller to control an offset adjuster configured to adjust an offset amount of the comparator; causing the controller to change the offset amount from a first value toward a second value and detect a third value when a logic level of a signal output from the comparator is changed; causing the controller to change the offset amount from the second value toward the first value and detect a fourth value when the logic level is changed; and causing the controller to detect the hysteresis characteristic of the comparator based on a first difference between the third value and the fourth value.

Abstract: A method for detecting a hysteresis characteristic of a comparator, include: causing a controller to control an offset adjuster configured to adjust an offset amount of the comparator; causing the controller to change the offset amount from a first value toward a second value and detect a third value when a logic level of a signal output from the comparator is changed; causing the controller to change the offset amount from the second value toward the first value and detect a fourth value when the logic level is changed; and causing the controller to detect the hysteresis characteristic of the comparator based on a first difference between the third value and the fourth value.

Abstract: A comparator includes an input-stage circuit that sets, in a first operating state, two voltage signals in a first voltage state, and changes, in a second operating state, the two voltage signals from the first voltage state to a second voltage state at different speeds, a latch-stage circuit that includes two field effect transistors and two inverters, the two field effect transistors receiving the two voltage signals at control nodes and disposed between two output nodes and a predetermined potential, the two inverters cross-coupled between the two output nodes and placed in an inactive state in the first operating state and in an active state in the second operating state, and a control circuit that controls current capacities in two paths through which drive voltages are applied to the two inverters, causing the current capacities to be different during at least part of a period of the second operating state.

Abstract: A charge transfer circuit has a charge transfer unit including an input charge holding element holding an input charge, an output charge holding element holding an output charge, and a charge transfer element, provided between a first node of the input charge holding element and a second, node of the output charge holding element, to transfer the charge held by the input charge holding element to the output charge holding element, an error sensing circuit detecting a third voltage corresponding to a first voltage of the first node when the charge transfer element finished transferring the charge from the input charge holding element to the output charge holding element, and an error correction unit correcting a second voltage of the second node when the charge transfer finished based on the third voltage and eliminate an error included in the second voltage of the second node.

Abstract: A CDR circuit includes an AD converter that converts an analog input signal to a digital output signal according to an operation clock signal; a phase adjuster that subtracts a first phase from a first clock signal having a first frequency equal to a frequency of the input signal to output a second clock signal having a second frequency as the operation clock signal to the AD converter; a phase detector that detects a second phase in the output signal of the AD converter; a filter that obtains a third phase by performing a filtering process based on the first phase, the second phase, and the third phase output from the filter; an adder that adds the first phase and the third phase to obtain a fourth phase; and a decision circuit that obtains recovered data from the output signal of the AD converter using the fourth phase.

Abstract: A CDR circuit includes an AD converter that converts an analog input signal to a digital output signal according to an operation clock signal; a phase adjuster that subtracts a first phase from a first clock signal having a first frequency equal to a frequency of the input signal to output a second clock signal having a second frequency as the operation clock signal to the AD converter; a phase detector that detects a second phase in the output signal of the AD converter; a filter that obtains a third phase by performing a filtering process based on the first phase, the second phase, and the third phase output from the filter; an adder that adds the first phase and the third phase to obtain a fourth phase; and a decision circuit that obtains recovered data from the output signal of the AD converter using the fourth phase.

Abstract: An analog/digital converter includes: a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period; a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; and a first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and wherein the second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage.

Abstract: An analog-digital converter apparatus includes a plurality of AD converters connected in series, each AD converter to convert an analog signal received by a first AD converter, at least one of the AD converters including: a residual signal generator that generates a first residual signal, the first residual signal being a difference between the analog signal or one of two residual signals amplified and output by a preceding AD converter and a first reference signal, and a second residual signal, the second residual signal being a difference between the analog signal or one of the two residual signals and a second reference signal; and an amplifier that amplifies and outputs the first residual signal to a subsequent AD converter at a first timing and amplifies and outputs the second residual signal to the subsequent AD converter at a second timing.