Patents by Inventor Yanfei CHEN

Yanfei CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8854243
    Abstract: A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: October 7, 2014
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Masato Yoshioka, Yanfei Chen, Tatsuya Ide
  • Patent number: 8854240
    Abstract: An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: October 7, 2014
    Assignee: Fujitsu Limited
    Inventors: Yanfei Chen, Sanroku Tsukamoto
  • Publication number: 20140184434
    Abstract: An analog/digital converter includes: a first analog/digital conversion unit that performs digital conversion on received first analog input voltage in a first time period; a second analog/digital conversion unit that performs digital conversion on received second analog input voltage in a second time period that is different from the first time period; and a first coupling capacitor that connects the first analog/digital conversion unit and the second analog/digital conversion unit, and wherein the second analog/digital conversion unit receives, through the first coupling capacitor, first residual voltage that is remaining voltage of the first analog input voltage on which digital conversion is performed in the first analog/digital conversion unit, as the second analog input voltage.
    Type: Application
    Filed: November 4, 2013
    Publication date: July 3, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Yanfei CHEN
  • Publication number: 20140125294
    Abstract: A charge transfer circuit has a charge transfer unit including an input charge holding element holding an input charge, an output charge holding element holding an output charge, and a charge transfer element, provided between a first node of the input charge holding element and a second, node of the output charge holding element, to transfer the charge held by the input charge holding element to the output charge holding element, an error sensing circuit detecting a third voltage corresponding to a first voltage of the first node when the charge transfer element finished transferring the charge from the input charge holding element to the output charge holding element, and an error correction unit correcting a second voltage of the second node when the charge transfer finished based on the third voltage and eliminate an error included in the second voltage of the second node.
    Type: Application
    Filed: January 10, 2014
    Publication date: May 8, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Yanfei CHEN
  • Publication number: 20130328709
    Abstract: An analogue-digital converter apparatus includes a plurality of AD converters connected in series, each AD converter to convert an analog signal received by a first AD converter, at least one of the AD converters including: a residual signal generator that generates a first residual signal, the first residual signal being a difference between the analog signal or one of two residual signals amplified and output by a preceding AD converter and a first reference signal, and a second residual signal, the second residual signal being a difference between the analog signal or one of the two residual signals and a second reference signal; and an amplifier that amplifies and outputs the first residual signal to a subsequent AD converter at a first timing and amplifies and outputs the second residual signal to the subsequent AD converter at a second timing.
    Type: Application
    Filed: May 1, 2013
    Publication date: December 12, 2013
    Applicant: FUJITSU LIMITED
    Inventor: Yanfei CHEN
  • Publication number: 20130321187
    Abstract: An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.
    Type: Application
    Filed: April 23, 2013
    Publication date: December 5, 2013
    Applicant: FUJITSU LIMITED
    Inventors: Yanfei CHEN, Sanroku TSUKAMOTO
  • Publication number: 20130321189
    Abstract: A low-power and high-speed ADC includes: a successive approximation converter circuit configured to sequentially compare and coarsely convert the analog input signal voltage into a digital signal with a number of higher-order bits, and also to output a residual voltage; a fixed-quantity change time measurement converter circuit configured to finely convert the residual voltage into a digital signal with a number n of lower-order bits by changing the residual voltage at a fixed rate of change and by measuring the time until a predetermined value is reached; and an encoder circuit configured to generate a digital signal with the predetermined number of bits by combining the digital signal with the number of higher-order bits output from the successive approximation converter circuit and the digital signal with the number of lower-order bits output from the fixed-quantity change time measurement converter circuit.
    Type: Application
    Filed: April 24, 2013
    Publication date: December 5, 2013
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: Masato YOSHIOKA, Yanfei Chen, Tatsuya Ide