Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.

Abstract: A display apparatus includes a panel, a backlight module, a cover, an integrated plastic frame and an optical adhesive. The panel is disposed over the backlight module. The cover is disposed over the panel, which is located between the cover and the backlight module. The integrated plastic frame includes a first accommodating portion, a second accommodating portion and an adhesive-restricting portion. The second accommodating portion is coupled between the first accommodating portion and the adhesive-restricting portion. The combination of the first accommodating portion, the second accommodating portion and the adhesive-restricting portion is integrally formed. The first accommodating portion accommodates at least a portion of the backlight module, the second accommodating portion accommodates the panel, and the adhesive-restricting portion is coupled between the second accommodating portion and the cover to define an accommodating space together with the cover and the panel.

Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

Abstract: A method and system are provided to determine an optimal placement with respect to position and orientation for one or more bones in a workspace of a robot to improve robotic cutting and maximize the robot workspace during a robotic surgical procedure. The method is additionally useful to aid a user in positioning and orienting the bones in the operating room at the determined position and orientation.

Abstract: A display apparatus includes a display module, a cover, a connecting element and an optical adhesive. The cover is disposed over the display module, and includes a cover portion and an adhesive-restricting portion. The adhesive-restricting portion is protruded from a periphery of a bottom side of the cover portion. The adhesive-restricting portion includes a lower surface facing a surface of the display module. The connecting element is connected between the lower surface of the adhesive-restricting portion and the surface of the display module, and defines an accommodating space together with the cover and the display module. The optical adhesive is disposed in the accommodating space.

Abstract: Various embodiments may provide a method of forming a semiconductor packaging structure. The method may include forming a plurality of semiconductor packages, each semiconductor package including a semiconductor die and a mold encapsulation structure. The method may also include arranging the plurality of semiconductor packages to form a vertical stacked arrangement with a mold portion including a plurality of mold encapsulation structures, the mold portion extending from a first side to a second side of the vertical stacked arrangement opposite the first side. The method may additionally include forming a first via on the mold portion at the first side of the vertical stacked arrangement, forming a second via on the mold portion at the second side of the vertical stacked arrangement, and forming an electrically conductive filled via extending through the mold portion from the first side to the second side of the vertical stacked arrangement.

Abstract: Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided. Embodiments include forming a first metal layer embedded between an upper and a lower portion of a PCB substrate, the first metal layer having a pair of metal filled vias laterally separated; attaching a semiconductor die to the upper portion of the PCB substrate between the pair of metal filled vias; connecting the semiconductor die electrically to the PCB substrate through the pair of metal filled vias; removing a portion of the upper portion of the PCB substrate outside of the pair of metal filled vias down to the first metal layer; and forming a second metal layer over and on four opposing sides of the semiconductor die, the second metal layer landed on the first metal layer.

Abstract: Various embodiments may provide a method of forming a semiconductor packaging structure. The method may include forming a plurality of semiconductor packages, each semiconductor package including a semiconductor die and a mold encapsulation structure. The method may also include arranging the plurality of semiconductor packages to form a vertical stacked arrangement with a mold portion including a plurality of mold encapsulation structures, the mold portion extending from a first side to a second side of the vertical stacked arrangement opposite the first side. The method may additionally include forming a first via on the mold portion at the first side of the vertical stacked arrangement, forming a second via on the mold portion at the second side of the vertical stacked arrangement, and forming an electrically conductive filled via extending through the mold portion from the first side to the second side of the vertical stacked arrangement.

Abstract: Methods of producing a fan-out wafer level package and the resulting device are provided. Embodiments include forming vias in a first surface of a carrier wafer; filling the vias with a metal; forming a redistribution layer (RDL) over the carrier wafer, the RDL being in contact with the metal filled vias; attaching a semiconductor die to the RDL; forming a wafer mold over the semiconductor die; and removing a portion of the carrier wafer to expose the metal filled vias on a second surface of the carrier wafer.

Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.

Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.

Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.

Abstract: Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided. Embodiments include forming a first metal layer embedded between an upper and a lower portion of a PCB substrate, the first metal layer having a pair of metal filled vias laterally separated; attaching a semiconductor die to the upper portion of the PCB substrate between the pair of metal filled vias; connecting the semiconductor die electrically to the PCB substrate through the pair of metal filled vias; removing a portion of the upper portion of the PCB substrate outside of the pair of metal filled vias down to the first metal layer; and forming a second metal layer over and on four opposing sides of the semiconductor die, the second metal layer landed on the first metal layer.

Abstract: Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided. Embodiments include forming a first metal layer embedded between an upper and a lower portion of a PCB substrate, the first metal layer having a pair of metal filled vias laterally separated; attaching a semiconductor die to the upper portion of the PCB substrate between the pair of metal filled vias; connecting the semiconductor die electrically to the PCB substrate through the pair of metal filled vias; removing a portion of the upper portion of the PCB substrate outside of the pair of metal filled vias down to the first metal layer; and forming a second metal layer over and on four opposing sides of the semiconductor die, the second metal layer landed on the first metal layer.

Abstract: Methods of magnetically shielding an MRAM structure on all six sides in a thin wire or thin flip chip bonding package and the resulting devices are provided. Embodiments include forming a first metal layer embedded between an upper and a lower portion of a PCB substrate, the first metal layer having a pair of metal filled vias laterally separated; attaching a semiconductor die to the upper portion of the PCB substrate between the pair of metal filled vias; connecting the semiconductor die electrically to the PCB substrate through the pair of metal filled vias; removing a portion of the upper portion of the PCB substrate outside of the pair of metal filled vias down to the first metal layer; and forming a second metal layer over and on four opposing sides of the semiconductor die, the second metal layer landed on the first metal layer.

Abstract: Disclosed is a power switching module for a battery module assembly in which a plurality of rectangular battery modules, each having a plurality of battery cells or unit modules connected in series to each other, are stacked in the width (longitudinal) and height (transverse) direction by at least twos such that the battery modules constitute a hexahedral structure (hexahedral stack), outer edges of the hexahedral stack are fixed by a frame member, and input and output terminals of the battery modules are oriented such that the input and output terminals of the battery modules are directed toward one surface (a) of the stack, wherein the power switching module comprises an insulative substrate mounted to the surface (a) of the stack, elements mounted on the substrate for controlling voltage and current during charge and discharge of the battery modules, and connection members mounted on the substrate for interconnecting the control elements.

Abstract: Disclosed herein is a battery module assembly configured to have a structure in which a plurality of rectangular battery modules, each of which has two or more battery cells or unit modules connected in series and/or in parallel to each other, are stacked by two or more in a width direction (a longitudinal direction) thereof and in a height direction (a transverse direction) thereof so that the rectangular battery modules generally constitute a hexahedral structure (a hexahedral stack), outer edges of the hexahedral stack are fixed by a frame member, and coupling parts for mounting, through which the battery module assembly is mounted to an external device, are provided at one side of the frame member.

Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

Abstract: A wafer level fan out semiconductor device and a manufacturing method thereof are provided. A first sealing part is formed on lateral surfaces of a semiconductor die. A plurality of redistribution layers are formed on surfaces of the semiconductor die and the first sealing part, and solder balls are attached to the redistribution layers. The solder balls are arrayed on the semiconductor die and the first sealing part. In addition, a second sealing part is formed on the semiconductor die, the first sealing part and lower portions of the solder balls. The solder balls are exposed to the outside through the second sealing part. Since the first sealing part and the second sealing part are formed of materials having thermal expansion coefficients which are the same as or similar to each other, warpage occurring to the wafer level fan out semiconductor device can be suppressed.

Abstract: Disclosed is a method for estimating the maximum power of a battery, which can inexpensively perform an estimation of the maximum power of a battery in a relatively simple manner of using the internal resistance of the battery, which has a correlation with and a largest effect on the maximum power of the battery. The method includes the steps of: measuring an internal resistance and a temperature of the battery and estimating a state of charge, if an estimation of the maximum power of the battery is requested; and reading a value of the maximum power of the battery, which corresponds to the measured temperature, the estimated state of charge, and the measured internal resistance, from a table in which the internal resistances and the maximum powers of the battery are mapped according to the temperatures and states of charge.