Abstract: A semiconductor package includes semiconductor dies, an encapsulant, a high-modulus dielectric layer and a redistribution structure. The encapsulant encapsulates the semiconductor dies and is made of a first material. The high-modulus dielectric layer extends on the encapsulant and the semiconductor dies. The high-modulus dielectric layer is made of a second material. The redistribution structure extends on the high-modulus dielectric layer. The redistribution structure includes conductive patterns embedded in at least a pair of dielectric layers. The dielectric layers of the pair are made of a third material. The elastic modulus of the first material is higher than the elastic modulus of the third material. The elastic modulus of the second material is higher than the elastic modulus of the third material.

Abstract: In example implementations, an apparatus is provided. The apparatus includes a dielectrophoresis (DEP) separator, an electrical field generator, a tracking system, and a controller. The DEP separator is to separate a plurality of different particles. The electrical field generator is coupled to the DEP separator to apply a frequency to the DEP separator. The tracking system is to track a movement of a type of particles in the DEP separator. The controller is in communication with the electrical field generator to control the frequency and the tracking system to track the separation. The controller is to calculate a cross-over frequency from a cross-over frequency distribution for the type of particles based on a frequency sweep performed on the type of particles and the movement of the type of particles that is tracked.

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.

Abstract: A device for simulating intermittent arc grounding faults in a power distribution network includes a sliding rail, a first and a second support frames, an insulated electrode disk, and an electrode disk motor. The first support frame is fixed on the left side of the slide rail, and the position of the second support frame relative to the first support frame can be adjusted through the sliding rail. The second support frame is provided with an electrode disk motor for driving the insulated electrode disk to rotate. An upper and a lower conductive bars are installed on the first support frame, their adjacent ends provided with an upper and a lower arc-shaped conductor sheets, and the insulated electrode disk having two circles of conductive pillars is located between the conductor sheets. The conductor sheets are respectively installed on the side of the conductive bars close to the conductive pillar.

Abstract: A method of recognizing an object includes comparing a three-dimensional point cloud of the object to a three-dimensional candidate from a dataset to determine a first confidence score, and comparing color metrics of a two-dimensional image of the object to a two-dimensional candidate from the dataset to determine a second confidence score. The point cloud includes a color appearance calibrated from a white balance image, and the color appearance of the object is compared with the three-dimensional candidate. The first or second confidence score is selected to determine which of the three-dimensional candidate or the two-dimensional candidate corresponds with the object.

Abstract: A deep learning method employs a neural network having three sub-nets to classify and retrieve the most similar 3D model of an object, given a rough 3D model or scanned images. The most similar 3D model is present in a database and can be retrieved to use directly or as a reference to redesign the 3D model. The three sub-nets of the neural network include one dealing with object images and the other two dealing with voxel representations. Majority vote is used instead of view pooling to classify the object. A feature map and a list of top N most similar well-designed 3D models are also provided.

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

Abstract: A three-dimensional object modeling method may include applying a nonrotating nonuniform electric field to apply a dielectrophoretic torque to a three-dimensional object to rotate the three-dimensional object, capturing images of the object at different angles during rotation of the object and forming a three-dimensional model of the object based on the captured images.

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming a plurality of contact pads over a substrate, and forming an insulating material over the plurality of contact pads and the substrate. The insulating material is patterned to form an opening over each of the plurality of contact pads, and the plurality of contact pads is cleaned. The method includes forming an under-ball metallization (UBM) structure over the plurality of contact pads and portions of the insulating material. Cleaning the plurality of contact pads recesses a top surface of each of the plurality of contact pads.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 16 weeks, alternatively no more than 12 weeks, or alternatively no more than 8 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 16, 12, or 8 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: A package structure includes a semiconductor die, an insulating encapsulant, a first redistribution layer, a second redistribution layer, antenna elements and a first insulating film. The insulating encapsulant is encapsulating the at least one semiconductor die, the insulating encapsulant has a first surface and a second surface opposite to the first surface. The first redistribution layer is disposed on the first surface of the insulating encapsulant. The second redistribution layer is disposed on the second surface of the insulating encapsulant. The antenna elements are located over the second redistribution layer. The first insulating film is disposed in between the second redistribution layer and the antenna elements, wherein the first insulating film comprises a resin rich region and a filler rich region, the resin rich region is located in between the filler rich region and the second redistribution layer and separating the filler rich region from the second redistribution layer.

Abstract: A method of manufacturing a semiconductor structure is provided. The method includes providing a first substrate including a plurality of conductive bumps disposed over the first substrate; providing a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; bonding the first substrate with the second substrate; and singulating a chip from the first substrate.

Abstract: A method of recognizing an object includes comparing a three-dimensional point cloud of the object to a three-dimensional candidate from a dataset to determine a first confidence score, and comparing color metrics of a two-dimensional image of the object to a two-dimensional candidate from the dataset to determine a second confidence score. The point cloud includes a color appearance calibrated from a white balance image, and the color appearance of the object is compared with the three-dimensional candidate. The first or second confidence score is selected to determine which of the three-dimensional candidate or the two-dimensional candidate corresponds with the object.

Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

Abstract: A method of manufacturing a semiconductor structure includes receiving a first substrate including an IMD layer disposed over the first substrate and a plurality of conductive bumps disposed in the IMD layer; receiving a second substrate; disposing a patterned adhesive over the first substrate, wherein at least a portion of the IMD layer is exposed through the patterned adhesive; and bonding the first substrate with the second substrate, wherein a top surface of the at least portion of the IMD layer is exposed through the patterned adhesive after bonding the first substrate with the second substrate.

Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.

Abstract: A method includes encapsulating a device in an encapsulating material, planarizing the encapsulating material and the device, and forming a conductive feature over the encapsulating material and the device. The formation of the conductive feature includes depositing a first conductive material to from a first seed layer, depositing a second conductive material different from the first conductive material over the first seed layer to form a second seed layer, plating a metal region over the second seed layer, performing a first etching on the second seed layer, performing a second etching on the first seed layer, and after the first seed layer is etched, performing a third etching on the second seed layer and the metal region.