Patents by Inventor Yang Wen

Yang Wen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139262
    Abstract: The present disclosure relates to a complex probiotic composition and a method for improving exercise performance of a subject with low intrinsic aerobic exercise capacity. The complex probiotic composition, which includes Lactobacillus rhamnosus GKLC1, Bifidobacterium lactis GKK24 and Clostridium butyricum GKB7, administered to the subject with the low intrinsic aerobic exercise capacity in a continuation period, can effectively reduce serum lactic acid and serum urea nitrogen after aerobic exercise, reduce proportion of offal fat and/or increase liver and muscle glycogen contents, thereby being as an effective ingredient for preparation of various compositions.
    Type: Application
    Filed: October 13, 2023
    Publication date: May 2, 2024
    Inventors: Chin-Chu CHEN, Yen-Lien CHEN, Shih-Wei LIN, Yen-Po CHEN, Ci-Sian WANG, Yu-Hsin HOU, Yang-Tzu SHIH, Ching-Wen LIN, Ya-Jyun CHEN, Jia-Lin JIANG, You-Shan TSAI, Zi-He WU
  • Publication number: 20240136312
    Abstract: A semiconductor device includes a first wafer having a deep trench capacitor and a second wafer bonded to the first wafer, in which the second wafer includes a first active device on a first silicon-on-insulator (SOI) substrate and a first metal interconnection connected to the first active device and the deep trench capacitor. The first wafer further includes the deep trench capacitor disposed in a substrate, a first inter-layer dielectric (ILD) layer on the deep trench capacitor, a first inter-metal dielectric (IMD) layer on the first ILD layer, and a second metal interconnection in the first ILD layer and the first IMD layer.
    Type: Application
    Filed: November 17, 2022
    Publication date: April 25, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, XINGXING CHEN
  • Patent number: 11957982
    Abstract: A game management system generates a multidimensional parametric player model representative of player behavior by one or more players in a computer game. The parametric player model populated is used in the identification of groups or clusters of players, and/or in at least partly automated configuration of custom game content for behavior consistent with the parametric player model. A single parametric player model is defines a single set of parametric values corresponding to multiple predefined gameplay parameters, and can be used to model the behavior of a single respective player or to model the behavior of multiple players (e.g., based on cumulative historical gameplay data for the relevant players), providing a representative player model for those players. The player model is ingested by a content generator configured to generate game content customized to the behavior represented by the player model.
    Type: Grant
    Filed: November 11, 2022
    Date of Patent: April 16, 2024
    Assignee: Zynga Inc.
    Inventors: Luke Dicken, Johnathan Pagnutti, Yang Wen
  • Publication number: 20240121771
    Abstract: A scheduling electronic device is used for selecting a candidate time-frequency resource set required for communication of a predetermined electronic device in the group to which the scheduling electronic device belongs; and the scheduling electronic device comprises a processing circuit, and the processing circuit is configured to: receive, from at least one member electronic device located in an overlapping region between said group and other groups, a cooperative sensing result obtained by sensing a time-frequency resource by the at least one member electronic device during at least a portion of a cooperative resource sensing window, so as to assist the scheduling electronic device in selecting a candidate time-frequency resource set, the cooperative resource sensing window being a time period for the at least one member electronic device to perform the assistance so as to sense the time-frequency resource.
    Type: Application
    Filed: April 12, 2022
    Publication date: April 11, 2024
    Applicant: Sony Group Corporation
    Inventors: Yanzhao HOU, Xiaofeng TAO, Yang WEN, Chengrui WANG, Yinan GUO, Xiaoxue WANG, Chen SUN
  • Patent number: 11955292
    Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: April 9, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, Xingxing Chen, Chao Jin
  • Patent number: 11948999
    Abstract: A device includes a first semiconductor fin, a second semiconductor fin, a source/drain epitaxial structure, a semiconductive cap, and a contact. The first semiconductor fin and the second semiconductor fin are over a substrate. The source/drain epitaxial structure is connected to the first semiconductor fin and the second semiconductor fin. The source/drain epitaxial structure includes a first protruding portion and a second protruding portion aligned with the first semiconductor fin and the second semiconductor fin, respectively. The semiconductive cap is on and in contact with the first protruding portion and the second protruding portion. A top surface of the semiconductive cap is lower than a top surface of the first protruding portion of the source/drain epitaxial structure. The contact is electrically connected to the source/drain epitaxial structure and covers the semiconductive cap.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 2, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Lilly Su, Yang-Tai Hsiao
  • Patent number: 11945016
    Abstract: Provided is an apparatus for fabricating a flexible display screen. The apparatus for the flexible display screen includes a roller mechanism and a jig, wherein the jig includes a bearing surface configured to bear a flexible display panel, the bearing surface being a curved surface; and the roller mechanism includes a roller, an axis of the roller being parallel to an element line of the bearing surface, and the roller being configured to roll on the bearing surface along a directrix of the bearing surface.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: April 2, 2024
    Assignees: MIANYANG BOE OPTOELECTRONICS TECHNOLOGY CO., Ltd., BOE Technology Group Co., Ltd.
    Inventors: Rongkun Fan, Yuanhong Wen, Peng Wang, Jialin Wang, Zhao Liang, Tao Zhang, Mu Zeng, Yang Wang, Jia Deng, Hongwei Cui
  • Patent number: 11945282
    Abstract: A gas detection and cleaning system for a vehicle is disclosed and includes an external modular base, a gas detection module and a cleaning device. The gas detection module is connected to a first external connection port of the external modular base to detect a gas in the vehicle and output the information datum. The information datum is transmitted through the first external connection port to a driving and controlling module of the external modular base, processed and converted into an actuation information datum for being externally outputted through a second external connection port of the external modular base. The cleaning device is connected with the second external connection port through an external port to receive the actuation information datum outputted from the second external connection port to actuate or close the cleaning device.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: April 2, 2024
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Yung-Lung Han, Chi-Feng Huang, Chin-Wen Hsieh, Tsung-I Lin, Yang Ku, Yi-Ting Lu
  • Patent number: 11939224
    Abstract: Provided are solid-state electrolyte structures. The solid-state electrolyte structures are ion-conducting materials. The solid-state electrolyte structures may be formed by 3-D printing using 3-D printable compositions. 3-D printable compositions may include ion-conducting materials and at least one dispersant, a binder, a plasticizer, or a solvent or any combination of one or more dispersant, binder, plasticizer, or solvent. The solid-state electrolyte structures can be used in electrochemical devices.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: March 26, 2024
    Assignee: University of Maryland, College Park
    Inventors: Eric D Wachsman, Dennis McOwen, Yunhui Gong, Yang Wen
  • Patent number: 11929213
    Abstract: A structure of capacitors connected in parallel includes a substrate. A trench embedded in the substrate. Numerous electrode layers respectively conformally fill in and cover the trench. The electrode layers are formed of numerous nth electrode layers, wherein n is a positive integer from 1 to M, and M is not less than 3. The nth electrode layer with smaller n is closer to the sidewall of the trench. When n equals to M, the Mth electrode layer fills in the center of the trench, and the top surface of the Mth electrode is aligned with the top surface of the substrate. A capacitor dielectric layer is disposed between the adjacent electrode layers. A first conductive plug contacts the nth electrode layer with odd-numbered n. A second conductive plug contacts the nth electrode layer with even-numbered n.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: March 12, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, Xingxing Chen, Chao Jin
  • Patent number: 11918329
    Abstract: A physiological detection device includes system including a first array PPG detector, a second array PPG detector, a display and a processing unit. The first array PPG detector is configured to generate a plurality of first PPG signals. The second array PPG detector is configured to generate a plurality of second PPG signals. The display is configured to show a detected result of the physiological detection system. The processing unit is configured to convert the plurality of first PPG signals and the plurality of second PPG signals to a first 3D energy distribution and a second 3D energy distribution, respectively, and control the display to show an alert message.
    Type: Grant
    Filed: April 23, 2021
    Date of Patent: March 5, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Chiung-Wen Lin, Wei-Ru Han, Yang-Ming Chou, Cheng-Nan Tsai, Ren-Hau Gu, Chih-Yuan Chuang
  • Patent number: 11923373
    Abstract: A semiconductor structure includes a semiconductor on insulator (SOI) substrate, a first electrically conductive structure, and a second electrically conductive structure. The SOI substrate includes a base substrate, a buried insulation layer disposed on the base substrate, a semiconductor layer disposed on the buried insulation layer, and a trap rich layer disposed between the buried insulation layer and the base substrate. At least a part of the first electrically conductive structure and at least a part of the second electrically conductive structure are disposed in the trap rich layer. A part of the trap rich layer is disposed between the first electrically conductive structure and the second electrically conductive structure. The first electrically conductive structure, the second electrically conductive structure, and the trap rich layer disposed between the first electrically conductive structure and the second electrically conductive structure are at least a portion of an anti-fuse structure.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: March 5, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Bo Tao, Li Wang, Ching-Yang Wen, Purakh Raj Verma, Zhibiao Zhou, Dong Yin, Gang Ren, Jian Xie
  • Publication number: 20240067566
    Abstract: A method for preparing Portland cement includes: respectively weighing iron slag, copper slag, vanadium slag, and nickel slag and grinding, to yield prefabricated iron slag, prefabricated copper slag, prefabricated vanadium slag, and prefabricated nickel slag; weighing mica and kaolinite, mixing, and grinding to obtain aluminous raw materials; evenly mixing the prefabricated iron slag and the aluminous raw materials, and calcining, to yield an iron-aluminum eutectic mineral; weighing the marble, fluorite, dolomite, and quartz, evenly mixing the marble, fluorite, dolomite, and quartz with the prefabricated copper slag, prefabricated vanadium slag, and prefabricated nickel slag to yield a first mixture; grinding the iron-aluminum eutectic mineral to yield powders, and calcining a second mixture of the first mixture and the powders, to yield the cement clinker; and cooling the cement clinker, and grinding a third mixture of the cooled cement clinker and the gypsum, to yield the Portland cement.
    Type: Application
    Filed: May 11, 2023
    Publication date: February 29, 2024
    Inventors: Kunyue ZHANG, Xiao ZHI, Min WANG, Zhaijun WEN, Xiaopeng AN, Wen HUANG, Guang YAO, Yang YU, Xin SHEN
  • Patent number: 11917348
    Abstract: A covering structure disposed within a sound producing package includes a first portion, a second portion and a third portion. The first portion is configured to form a first sound outlet having a first diameter. The second portion is configured to form a chamber having a second diameter. The third portion is configured to form a second sound outlet having a third diameter. Wherein, the first sound outlet, the chamber and the second sound outlet provide an acoustic pathway, the first diameter is smaller than the second diameter, and the third diameter is smaller than the second diameter; and wherein, the second portion is disposed between the first portion and the third portion.
    Type: Grant
    Filed: May 4, 2022
    Date of Patent: February 27, 2024
    Assignee: XMEMS TAIWAN CO., LTD.
    Inventors: Hai-Hung Wen, Wei-Yang Li
  • Patent number: 11916110
    Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.
    Type: Grant
    Filed: July 4, 2022
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Ching Wang, Wei-Yang Lee, Ming-Chang Wen, Jo-Tzu Hung, Wen-Hsing Hsieh, Kuan-Lun Cheng
  • Publication number: 20240053959
    Abstract: Aspects of the present disclosure involve a system comprising a computer-readable storage medium storing a program and method for automatic quantization of a floating point model. The program and method provide for providing a floating point model to an automatic quantization library, the floating point model being configured to represent a neural network, and the automatic quantization library being configured to generate a first quantized model based on the floating point model; providing a function to the automatic quantization library, the function being configured to run a forward pass on a given dataset for the floating point model; causing the automatic quantization library to generate the first quantized model based on the floating point model; causing the automatic quantization library to calibrate the first quantized model by running the first quantized model on the function; and converting the calibrated first quantized model to a second quantized model.
    Type: Application
    Filed: June 8, 2023
    Publication date: February 15, 2024
    Inventors: Denys Makoviichuk, Jiazhuo Wang, Yang Wen
  • Publication number: 20240050859
    Abstract: A game management system provides a content generator configured for automated generation of custom game content based on a plurality of parametric values that model gameplay behavior of one or more players for whom the game content is to be customized. The customized configuration is generated in a predefined sequence of progressive configuration stages. In each stage, a respective configurable feature is assigned a custom value that is determined (e.g., in a biased or constrained randomized operation) based on a respectively linked parameter value from the data model.
    Type: Application
    Filed: July 3, 2023
    Publication date: February 15, 2024
    Inventors: Luke Dicken, Johnathan Pagnutti, Yang Wen
  • Publication number: 20240047266
    Abstract: A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Liang Liao, Chee Hau Ng, Ching-Yang Wen, Purakh Raj Verma
  • Publication number: 20240038832
    Abstract: A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.
    Type: Application
    Filed: August 21, 2022
    Publication date: February 1, 2024
    Applicant: United Microelectronics Corp.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, Chee-Hau Ng, Chin-Wei Ho
  • Patent number: 11881529
    Abstract: A method of fabricating a semiconductor device is provided. First, a semiconductor structure is provided, and the semiconductor structure includes a buried dielectric layer, a first gate structure disposed on a front-side of the buried dielectric layer, and a first source/drain region and a second source/drain region disposed between the buried dielectric layer and the first gate structure. Then, a trench is formed in the buried dielectric layer. Afterwards, a conductive layer is formed on the buried dielectric layer and in the trench. Finally, the conductive layer is patterned.
    Type: Grant
    Filed: September 5, 2022
    Date of Patent: January 23, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Ching-Yang Wen, Li Wang, Kai Cheng