Patents by Inventor Yaniv Fais
Yaniv Fais has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240119255Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.Type: ApplicationFiled: December 21, 2023Publication date: April 11, 2024Applicant: Intel CorporationInventors: Yaniv Fais, Moshe Maor
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Publication number: 20240112033Abstract: In an example, an apparatus comprises at least one execution platform; and logic, at least partially including hardware logic, to receive a trained neural network model in a model optimizer and convert the trained neural network model to an optimized model comprising parameters that are fit to the at least one execution platform. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: November 20, 2023Publication date: April 4, 2024Applicant: Intel CorporationInventors: Amit Bleiweiss, Itamar Ben-Ari, Michael Behar, Guy Jacob, Gal Leibovich, Jacob Subag, Lev Faivishevsky, Yaniv Fais, Tomer Schwartz
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Patent number: 11886984Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.Type: GrantFiled: August 10, 2021Date of Patent: January 30, 2024Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Amit Bleiweiss, Gal Leibovich, Jeremie Dreyfuss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag
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Publication number: 20240028883Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.Type: ApplicationFiled: July 26, 2023Publication date: January 25, 2024Applicant: Intel CorporationInventors: Tomer Schwartz, Ehud Cohen, Uzi Sarel, Amitai Armon, Yaniv Fais, Lev Faivishevsky, Amit Bleiweiss, Yahav Shadmiy, Jacob Subag
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Publication number: 20230394305Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: May 30, 2023Publication date: December 7, 2023Applicant: Intel CorporationInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz, Raanan Yonatan Yehezkel Rohekar, Michael Behar, Amitai Armon, Uzi Sarel
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Publication number: 20230316589Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: March 28, 2023Publication date: October 5, 2023Applicant: Intel CorporationInventors: Tomer Bar-On, Jacob Subag, Yaniv Fais, Jeremie Dreyfuss, Gal Novik, Gal Leibovich, Tomer Schwartz, Ehud Cohen, Lev Faivishevsky, Uzi Sarel, Amitai Armon, Yahav Shadmiy
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Patent number: 11763140Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.Type: GrantFiled: August 5, 2021Date of Patent: September 19, 2023Assignee: INTEL CORPORATIONInventors: Tomer Schwartz, Ehud Cohen, Uzi Sarel, Amitai Armon, Yaniv Fais, Lev Faivishevsky, Amit Bleiweiss, Yahav Shadmiy, Jacob Subag
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Publication number: 20230281435Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 24, 2023Publication date: September 7, 2023Applicant: Intel CorporationInventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsch, Orly Weisel, Zigi Walter, Yarden Oren
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Patent number: 11704564Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: GrantFiled: August 17, 2021Date of Patent: July 18, 2023Assignee: INTEL CORPORATIONInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz, Raanan Yonatan Yehezkel Rohekar, Michael Behar, Amitai Armon, Uzi Sarel
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Patent number: 11669719Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 12, 2021Date of Patent: June 6, 2023Assignee: INTEL CORPORATIONInventors: Jeremie Dreyfuss, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Eran Ben-Avi, Neta Zmora, Tomer Schwartz
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Patent number: 11656846Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: GrantFiled: November 24, 2020Date of Patent: May 23, 2023Assignee: INTEL CORPORATIONInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
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Patent number: 11620766Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer.Type: GrantFiled: June 10, 2021Date of Patent: April 4, 2023Assignee: INTEL CORPORATIONInventors: Tomer Bar-On, Jacob Subag, Yaniv Fais, Jeremie Dreyfuss, Gal Novik, Gal Leibovich, Tomer Schwartz, Ehud Cohen, Lev Faivishevsky, Uzi Sarel, Amitai Armon, Yahav Shadmiy
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Patent number: 11600035Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: GrantFiled: February 10, 2022Date of Patent: March 7, 2023Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
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Patent number: 11599777Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 28, 2017Date of Patent: March 7, 2023Assignee: Intel CorporationInventors: Eran Ben-Avi, Neta Zmora, Guy Jacob, Lev Faivishevsky, Jeremie Dreyfuss, Tomer Bar-On, Jacob Subag, Yaniv Fais, Shira Hirsch, Orly Weisel, Zigi Walter, Yarden Oren
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Publication number: 20230067421Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.Type: ApplicationFiled: September 28, 2022Publication date: March 2, 2023Inventors: Yaniv Fais, Moshe Maor
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Publication number: 20230046558Abstract: A method, integrated circuit, and a computer readable medium that stores instructions for reducing IO traffic from a global or remote memory unit to a buffer of a neural network unit, by using overlap rows of an input feature map tile.Type: ApplicationFiled: August 10, 2022Publication date: February 16, 2023Inventors: Orly Weisel, Yaniv FAIS, Shira HIRSCH
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Publication number: 20220366534Abstract: The present subject matter provides technical solutions facing technical problems associated with preserving spatial dimension of images used in CNNs. Transposed convolutional layers may be used to provide improved spatial dimension preservation or reconstruction. In contrast with image interpolation, transposed convolutional layers may use a set of weights to reconstruct input images. When using CNNs for ADAS and AV applications, the transposed convolutional layers may be trained jointly with convolutional layers during the CNN training process. This may provide the ability to use a lower-dimensional representation of input images, while preserving the spatial dimension of images for use in ADAS and AV systems.Type: ApplicationFiled: May 9, 2022Publication date: November 17, 2022Inventors: Yaniv FAIS, Ariel Binenfeld, Liran Levy
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Publication number: 20220366215Abstract: A method for neural network convolution, the method may include receiving input data that is a 3D input data and comprises input data segments associated with different input data depth values; receiving a convolution kernel that is a 3D convolution kernel and comprises kernel segments associated with different kernel depth values; performing multiple 3D convolution iteration, wherein each of 3D convolution iteration comprises: determining whether the 3D convolution iteration is of a first type or of a second type; executing the 3D convolution iteration of the first type when determining that the 3D convolution iteration is of the first type; and executing the 3D convolution iteration of the second type when determining that the 3D convolution iteration is of the second type.Type: ApplicationFiled: May 9, 2022Publication date: November 17, 2022Inventors: Orly WEISEL, Yaniv FAIS, Shira HIRSCH, Daniel SREBNIK
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Patent number: 11494608Abstract: An example apparatus to perform a convolution on an input tensor includes a parameters generator to: generate a horizontal hardware execution parameter for a horizontal dimension of the input tensor based on a kernel parameter and a layer parameter; and generate a vertical hardware execution parameter for a vertical dimension of the input tensor based on the kernel parameter and the layer parameter; an accelerator interface to configure a hardware accelerator circuitry based on the horizontal and vertical hardware execution parameters; a horizontal Iterator controller to determine when the hardware accelerator circuitry completes the first horizontal iteration of the convolution; and a vertical Iterator controller to determine when the hardware accelerator circuitry completes the first vertical iteration of the convolution.Type: GrantFiled: August 14, 2019Date of Patent: November 8, 2022Assignee: Intel CorporationInventors: Yaniv Fais, Moshe Maor
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Publication number: 20220237850Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 10, 2022Publication date: July 28, 2022Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss