Patents by Inventor Yaniv Fais
Yaniv Fais has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20220237850Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 10, 2022Publication date: July 28, 2022Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
-
Publication number: 20220222317Abstract: An improved convolution kernel system and method may be used to improve performance of analysis of input image data for autonomous or semi-autonomous vehicle navigation. A processing circuit may be used to apply a convolution kernel on the input data to provide output data that comprises output data segments. The application may include repeating scanning and summing, including parallel scanning input data segments of the different input channels and of the input data depth value to provide first intermediate results associated with the input data depth value, and summing first intermediate results associated with a same output data channel and with different input depth values to provide, per each output data channel, a second result. The output analyzed image data may be used to generate a vehicle control signal, such as automatic control of braking, acceleration, or steering of a vehicle.Type: ApplicationFiled: December 30, 2021Publication date: July 14, 2022Inventors: Orly Weisel, Yaniv Fais, Arik Gaon
-
Publication number: 20220215226Abstract: A method for neural network processing, the method may include applying, by a neural network processor, a group of neural network kernels of respective layers of a neural network to provide neural network output results. The applying may include applying a (2D) kernel of the group of kernels on 2D layer input values of a first layer of the neural network to provide first layer output values. The applying may include scanning the 2D layer input values with the 2D kernel. The scanning may include flattening the 2D kernel, flattening the 2D layer input values, and storing first layer output values in a 3D memory unit. The applying may also include applying a 3D kernel of the group of kernels, on 3D layer input values of a second layer of the neural network to provide second layer output values, wherein the applying comprises scanning at least one feature vector of the 3D layer input values with at least one vector of the 3D kernel.Type: ApplicationFiled: December 20, 2021Publication date: July 7, 2022Inventors: Yaniv Fais, Avner Strum, Liran Levy
-
Publication number: 20220076118Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 17, 2021Publication date: March 10, 2022Applicant: Intel CorporationInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz, Raanan Yonatan Yehezkel Rohekar, Michael Behar, Amitai Armon, Uzi Sarel
-
Publication number: 20220067496Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 10, 2021Publication date: March 3, 2022Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Amit Bleiweiss, Gal Leibovich, Jeremie Dreyfuss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag
-
Publication number: 20220058469Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.Type: ApplicationFiled: August 5, 2021Publication date: February 24, 2022Applicant: Intel CorporationInventors: TOMER SCHWARTZ, Ehud Cohen, Uzi Sarel, Amitai Armon, Yaniv Fais, Lev Faivishevsky, Amit Bleiweiss, Yahav Shadmiy, Jacob Subag
-
Patent number: 11250610Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: GrantFiled: August 28, 2020Date of Patent: February 15, 2022Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
-
Patent number: 11238338Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 24, 2017Date of Patent: February 1, 2022Assignee: INTEL CORPORATIONInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz, Raanan Yonatan Yehezkel Rohekar, Michael Behar, Amital Armon, Uzi Sarel
-
Publication number: 20210350585Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: June 10, 2021Publication date: November 11, 2021Applicant: INTEL CORPORATIONInventors: Tomer Bar-On, Jacob Subag, Yaniv Fais, Jeremie Dreyfuss, Gal Novik, Gal Leibovich, Tomer Schwartz, Ehud Cohen, Lev Faivishevsky, Uzi Sarel, Amitai Armon, Yahav Shadmiy
-
Patent number: 11132601Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 24, 2017Date of Patent: September 28, 2021Assignee: INTEL CORPORATIONInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz
-
Patent number: 11100393Abstract: In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 24, 2017Date of Patent: August 24, 2021Assignee: INTEL CORPORATIONInventors: Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Jeremie Dreyfuss, Amit Bleiweiss, Tomer Schwartz
-
Publication number: 20210256272Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: February 12, 2021Publication date: August 19, 2021Applicant: Intel CorporationInventors: Jeremie Dreyfuss, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Eran Ben-Avi, Neta Zmora, Tomer Schwartz
-
Patent number: 11093822Abstract: In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 28, 2017Date of Patent: August 17, 2021Assignee: INTEL CORPORATIONInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Amit Bleiweiss, Gal Leibovich, Jeremie Dreyfuss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag
-
Patent number: 11087206Abstract: A mechanism is described for facilitating memory handling and data management in machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting multiple tables associated with multiple neural networks at multiple autonomous machines, where each of the multiple tables include an index. The method may further include combining the multiple tables and multiple indexes associated with the multiple tables into a single table and a single index, respectively, where the single table is communicated to the multiple autonomous machines to allow simultaneous processing of one or more portions of the single table using one or more memory devices and one or more processors of one or more of the multiple autonomous machines.Type: GrantFiled: April 28, 2017Date of Patent: August 10, 2021Assignee: INTEL CORPORATIONInventors: Tomer Schwartz, Ehud Cohen, Uzi Sarel, Amitai Armon, Yaniv Fais, Lev Faivishevsky, Amit Bleiweiss, Yahav Shadmiy, Jacob Subag
-
Patent number: 11037330Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 8, 2017Date of Patent: June 15, 2021Assignee: INTEL CORPORATIONInventors: Tomer Bar-On, Jacob Subag, Yaniv Fais, Jeremie Dreyfuss, Gal Novik, Gal Leibovich, Tomer Schwartz, Ehud Cohen, Lev Faivishevsky, Uzi Sarel, Amitai Armon, Yahav Shadmiy
-
Publication number: 20210141604Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: November 24, 2020Publication date: May 13, 2021Applicant: Intel CorporationInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby
-
Patent number: 10990399Abstract: Methods and apparatus to implement efficient communications between components of computing systems are disclosed. An example apparatus includes a message generator to: add a first value associated with a first field of a message to a shift register based on a first push operation, the message including multiple fields, at least two of the fields having different bit widths; and add a second value associated with a second field of the message to the shift register based on a second push operation, the second value to be adjacent the first value in the shift register in accordance with a structure of the message. The example apparatus further includes a communications interface to transmit content stored in the shift register to a hardware device via a bus having a width corresponding to a width of the shift register, the content including the message.Type: GrantFiled: August 13, 2019Date of Patent: April 27, 2021Assignee: Intel CorporationInventors: Moshe Maor, Yaniv Fais
-
Publication number: 20210049804Abstract: In an example, an apparatus comprises a plurality of execution units; and logic, at least partially including hardware logic, to determine a sub-graph of a network that can be executed in a frequency domain and apply computations in the sub-graph in the frequency domain. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: August 28, 2020Publication date: February 18, 2021Applicant: Intel CorporationInventors: Uzi Sarel, Ehud Cohen, Tomer Schwartz, Amitai Armon, Yahav Shadmiy, Itamar Ben-Ari, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Michael Behar, Guy Jacob, Gal Leibovich, Jeremie Dreyfuss
-
Patent number: 10922556Abstract: In an example, an apparatus comprises logic, at least partially including hardware logic, to save one or more outputs of a deep learning neural network in a storage system of an autonomous vehicle and upload the one or more outputs to a remote server. Other embodiments are also disclosed and claimed.Type: GrantFiled: April 28, 2017Date of Patent: February 16, 2021Assignee: INTEL CORPORATIONInventors: Jeremie Dreyfuss, Amit Bleiweiss, Lev Faivishevsky, Tomer Bar-On, Yaniv Fais, Jacob Subag, Eran Ben-Avi, Neta Zmora, Tomer Schwartz
-
Patent number: 10853035Abstract: In an example, an apparatus comprises a plurality of execution units and logic, at least partially including hardware logic, to gate at least one of a multiply unit or an accumulate unit in response to an input of value zero. Other embodiments are also disclosed and claimed.Type: GrantFiled: March 27, 2020Date of Patent: December 1, 2020Assignee: INTEL CORPORATIONInventors: Yaniv Fais, Tomer Bar-On, Jacob Subag, Jeremie Dreyfuss, Lev Faivishevsky, Michael Behar, Amit Bleiweiss, Guy Jacob, Gal Leibovich, Itamar Ben-Ari, Galina Ryvchin, Eyal Yaacoby