Patents by Inventor Yao-Ching Ku
Yao-Ching Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110289466Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.Type: ApplicationFiled: August 2, 2011Publication date: November 24, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
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Patent number: 8037575Abstract: An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.Type: GrantFiled: September 16, 2008Date of Patent: October 18, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Chou Cheng, Chih-Ming Lai, Ru-Gun Liu, Tsong-Hua Ou, Min-Hong Wu, Yih-Yuh Doong, Hsiao-Shu Chao, Yi-Kan Cheng, Yao-Ching Ku, Cliff Hou
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Publication number: 20110231804Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.Type: ApplicationFiled: May 26, 2011Publication date: September 22, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Publication number: 20110230998Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.Type: ApplicationFiled: May 26, 2011Publication date: September 22, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Publication number: 20110217630Abstract: An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.Type: ApplicationFiled: March 11, 2011Publication date: September 8, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd., ("TSMC")Inventors: George Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
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Patent number: 8001494Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.Type: GrantFiled: October 13, 2008Date of Patent: August 16, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yung-Chin Hou, Ying-Chou Cheng, Ru-Gun Liu, Chih-Ming Lai, Yi-Kan Cheng, Chung-Kai Lin, Hsiao-Shu Chao, Ping-Heng Yeh, Min-Hong Wu, Yao-Ching Ku, Tsong-Hua Ou
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Patent number: 7954072Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.Type: GrantFiled: May 15, 2007Date of Patent: May 31, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Publication number: 20100293514Abstract: A method of designing an integrated circuit (“IC”) is provided that includes placing an IC design, where the IC design includes a first element, a second element, and a path coupling the first and second elements, and routing the IC design. Further, the method includes obtaining at least one of resistivity data and capacitance data related to the path, and obtaining timing data related to the path. The method also includes using at least one of the resistivity data, the capacitance data, and the timing data to determine a critical dimension (“CD”) bias to be applied to the path, and modifying the IC design, where modifying includes applying the CD bias to the path.Type: ApplicationFiled: May 12, 2009Publication date: November 18, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Louis Chao-Chiuan Liu, Lee-Chung Lu, Yao-Ching Ku
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Patent number: 7783999Abstract: A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.Type: GrantFiled: January 18, 2008Date of Patent: August 24, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsong-Hua Ou, Ying-Chou Cheng, Chia-Chi Lin, Ru-Gun Liu, Chih-Ming Lai, Min-Hong Wu, Yih-Yuh Doong, Cliff Hou, Yao-Ching Ku
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Patent number: 7778805Abstract: An optimized optical proximity correction modeling method comprises receiving a selection of a regression method, displaying regression parameters, receiving values for the displayed regression parameters, receiving a selection of an optimization method, displaying optimization parameters, receiving values for the displayed optimization parameters, and generating an optimized optical proximity correction output.Type: GrantFiled: July 28, 2005Date of Patent: August 17, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen Chun Huang, Ru-Gun Liu, Chih-Ming Lai, Chen Kun Tsai, Chien Wen Lai, Cherng-Shyan Tsay, Cheng Cheng Kuo, Yao-Ching Ku
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Patent number: 7727682Abstract: System and method for providing a passivation layer for a phase shift mask (“PSM”) are described. In one embodiment, a PSM comprises a transparent substrate; a phase shift pattern disposed on the transparent substrate; and a passivation layer disposed to substantially cover exposed surfaces of at least a portion of the phase shift pattern.Type: GrantFiled: March 21, 2007Date of Patent: June 1, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Ting Pan, Ken Wu, Luke Hsu, Yao-Ching Ku
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Publication number: 20100095253Abstract: Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.Type: ApplicationFiled: October 13, 2008Publication date: April 15, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yung-Chin HOU, Ying-Chou CHENG, Ru-Gun LIU, Chih-Ming LAI, Yi-Kan CHENG, Chung-Kai LIN, Hsiao-Shu CHAO, Ping-Heng YEH, Min-Hong WU, Yao-Ching KU, Tsong-Hua OU
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Patent number: 7685558Abstract: A method for detection and scoring of hotspots in a design layout is provided. A plurality of indices is derived for a plurality of positions in the design layout. The plurality of indices comprises a first index sensitive to energy exposure of the design layout, a second index sensitive to process image formation, and a third index sensitive to mask manufacturing error. The plurality of indices is then analyzed to identify at least one hotspot in the design layout. The at least one hotspot is then prioritized using an integrated hotspot scoring system. The integrated hotspot scoring system prioritizes hotspots based on a look-up table approach or an interpolation approach.Type: GrantFiled: March 6, 2007Date of Patent: March 23, 2010Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Ming Lai, Ru-Gun Liu, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Publication number: 20090258159Abstract: A method includes forming an absorption material layer on a mask; applying a plasma treatment to the mask to reduce chemical contaminants after the forming of the absorption material layer; performing a chemical cleaning process of the mask; and performing a gas injection to the mask.Type: ApplicationFiled: April 10, 2008Publication date: October 15, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yih-Chen Su, Ting-Hao Hsu, Sheng-Chi Chin, Heng-Jen Lee, Hung Chang Hsieh, Yao-Ching Ku
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Publication number: 20090222785Abstract: An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.Type: ApplicationFiled: September 16, 2008Publication date: September 3, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ying-Chou CHENG, Chih-Ming LAI, Ru-Gun LIU, Tsong-Hua OU, Min-Hong WU, Yih-Yuh DOONG, Hsiao-Shu CHAO, Yi-Kan CHENG, Yao-Ching KU, Cliff HOU
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Publication number: 20090206057Abstract: A method and system for fabricating a substrate is disclosed. First, a plurality of process chambers are provided, at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate and at least one of the plurality of process chambers containing a plasma filtering plate library. A plasma filtering plate is selected and removed from the plasma filtering plate library. Then, the plasma filtering plate is inserted into at least one of the plurality of process chambers adapted to receive at least one plasma filtering plate. Subsequently, an etching process is performed in the substrate.Type: ApplicationFiled: February 14, 2008Publication date: August 20, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Hsiung Huang, Chi-Lun Lu, Heng-Jen Lee, Sheng-Chi Chin, Yao-Ching Ku
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Publication number: 20090187866Abstract: A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.Type: ApplicationFiled: January 18, 2008Publication date: July 23, 2009Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsong-Hua Ou, Ying-Chou Cheng, Chia-Chi Lin, Ru-Gun Liu, Chih-Ming Lai, Min-Hong Wu, Yih-Yuh Doong, Cliff Hou, Yao-Ching Ku
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Publication number: 20080233486Abstract: System and method for providing a passivation layer for a phase shift mask (“PSM”) are described. In one embodiment, a PSM comprises a transparent substrate; a phase shift pattern disposed on the transparent substrate; and a passivation layer disposed to substantially cover exposed surfaces of at least a portion of the phase shift pattern.Type: ApplicationFiled: March 21, 2007Publication date: September 25, 2008Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hung-Ting Pan, Ken Wu, Luke Hsu, Yao-Ching Ku
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Patent number: 7387969Abstract: A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing the hardmask and resist to form a patterned resist and patterned hardmask.Type: GrantFiled: March 18, 2005Date of Patent: June 17, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: George Liu, Vencent Chang, Norman Chen, Yao-Ching Ku, Chin-Hsiang Lin, Kuei Shun Chen
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Patent number: 7314689Abstract: A method and system is disclosed for processing one or more oblique features on a mask or reticle substrate. After aligning the mask or reticle substrate with a predetermined reference system, an offset angle of a feature to be processed on the mask or reticle substrate with regard to either the horizontal or vertical reference direction of the predetermined reference system is determined. The mask or reticle substrate is rotated in a predetermined direction by the offset angle; and the feature on the mask or reticle substrate is processed using the predetermined reference system wherein the feature is processed in either the horizontal or vertical reference direction thereof.Type: GrantFiled: January 27, 2004Date of Patent: January 1, 2008Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Burn Jeng Lin, Ping Yang, Hong Chang Hsieh, Yao Ching Ku, Chin Hsian Lin, Chiu Shan Yoo