Patents by Inventor Yao-Ching Ku
Yao-Ching Ku has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20070265725Abstract: Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.Type: ApplicationFiled: May 15, 2007Publication date: November 15, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ru-Gun Liu, Chih-Ming Lai, Wen-Chun Huang, Boren Luo, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Publication number: 20070266362Abstract: A method for detection and scoring of hotspots in a design layout is provided. A plurality of indices is derived for a plurality of positions in the design layout. The plurality of indices comprises a first index sensitive to energy exposure of the design layout, a second index sensitive to process image formation, and a third index sensitive to mask manufacturing error. The plurality of indices is then analyzed to identify at least one hotspot in the design layout. The at least one hotspot is then prioritized using an integrated hotspot scoring system. The integrated hotspot scoring system prioritizes hotspots based on a look-up table approach or an interpolation approach.Type: ApplicationFiled: March 6, 2007Publication date: November 15, 2007Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Ming Lai, Ru-Gun Liu, I-Chang Shin, Yao-Ching Ku, Cliff Hou
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Patent number: 7218400Abstract: A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.Type: GrantFiled: March 3, 2004Date of Patent: May 15, 2007Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Grace H. Ho, Ming-Che Wu, Li-Heng Chou, Hung-Chang Hsieh, Jung Ting Chen, Yao-Ching Ku
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Publication number: 20070038417Abstract: An optimized optical proximity correction modeling method comprises receiving a selection of a regression method, displaying regression parameters, receiving values for the displayed regression parameters, receiving a selection of an optimization method, displaying optimization parameters, receiving values for the displayed optimization parameters, and generating a optimized optical proximity correction output.Type: ApplicationFiled: July 28, 2005Publication date: February 15, 2007Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen Chun Huang, Ru-Gun Liu, Chih-Ming Lai, Chen Tsai, Chien Lai, Cherng-Shyan Tsay, Cheng Cheng Kuo, Yao-Ching Ku
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Publication number: 20060211254Abstract: A patterned hardmask and method for forming the same, the method including providing a substrate comprising an overlying resist sensitive to activating radiation; forming an overlying hardmask insensitive to the activating radiation; exposing the resist through the hardmask to the activating radiation; baking the resist and the hardmask; and, developing the hardmask and resist to form a patterned resist and patterned hardmask.Type: ApplicationFiled: March 18, 2005Publication date: September 21, 2006Inventors: George Liu, Vencent Chang, Norman Chen, Yao-Ching Ku, Chin-Hsiang Lin, Kuei Chen
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Patent number: 6979820Abstract: A method and apparatus for scanning electron microscope measurements which maintains a constant e-beam dose to the surface of a wafer being measured and thereby maintains a constant resist shrinkage. The apparatus provides a magnetic lens, a movable wafer holder to adjust the distance between a wafer and the magnetic lens, an image detector, means to determine the distance between the wafer and the magnetic lens, a retarding voltage applied to the wafer holder, means to adjust the retarding voltage, and means to focus the magnetic lens. The apparatus also provides feedback systems between the movable wafer holder and the means to determine the distance between the wafer and the magnetic lens, between the image detector and the means to adjust the retarding voltage, and between the image detector and means to focus the magnetic lens so these adjustments can be made automatically. The method first sets the distance between the wafer and the magnetic lens.Type: GrantFiled: July 29, 2003Date of Patent: December 27, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Ming Ke, Chien-Hsun Lin, Yao-Ching Ku
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Publication number: 20050195397Abstract: A semiconductor wafer is disclosed that includes a plurality of fields, including a plurality of alignment fields. Each alignment field includes a plurality of intra-field small scribe lane primary mark (SSPM) overlay mark pairs there around. The SSPM mark pairs allow for in-situ, non-passive intra-field alignment correction. In one embodiment, there may be between two and four alignment fields, and between two and four SSPM mark pairs around each alignment field. The SSPM marks of each mark pair may be extra scribe-lane marks.Type: ApplicationFiled: March 3, 2004Publication date: September 8, 2005Inventors: Grace Ho, Ming-Che Wu, Li-Heng Chou, Hung-Chang Hsieh, Jung Chen, Yao-Ching Ku
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Publication number: 20050023463Abstract: Reducing photoresist shrinkage by plasma treatment is disclosed. A semiconductor wafer having one or more photoresist layers is plasma treated, such as plasma curing, plasma etching, and/or high-density plasma etching the wafer. After plasma treating, one or more critical dimensions on the photoresist layers is measured using an electron beam, such as by using a scanning electron microscope (SEM). The plasma treating of the wafer prior to measuring the critical dimensions using the electron beam decreases shrinkage of the photoresist layer when using the electron beam.Type: ApplicationFiled: July 29, 2003Publication date: February 3, 2005Inventors: Chih-Ming Ke, Chien-Hsun Lin, Yao-Ching Ku
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Patent number: 6492073Abstract: A mask set of two masks and a method of using these masks in a double exposure to avoid line shortening due to optical proximity effects is described. A pattern having pattern elements comprising a number of line segments, wherein each of the line segments has one or two free ends which are not connected to other mask pattern elements is to be transferred to a layer of resist. A first mask is formed by adding line extensions to each of the free ends of the line segments. A cutting mask is formed comprising rectangles enclosing each of the line extensions wherein one of the sides of said rectangles is coincident with the corresponding free end of said line segment. The first mask has opaque regions corresponding to the extended line segments. The cutting mask has transparent regions corresponding to the cutting pattern. In another embodiment a pattern having pattern openings comprising a number of line segments.Type: GrantFiled: April 23, 2001Date of Patent: December 10, 2002Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Burn Jeng Lin, Ru-Gun Liu, Shih-Ying Chen, Shinn-Sheng Yu, Hua-Tai Lin, Anthony Yen, Yao-Ching Ku
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Publication number: 20020064716Abstract: A method of optical proximity correction suitable for use in a mixed mode photomask. An original pattern is to be transferred from the mixed mode photomask. A binary mask curve and a phase shift mask curve reflecting relationship between critical dimensions of the photomask and the original pattern are obtained. A critical value of the critical dimension is selected. For the binary mask curve, the portion with the critical dimension of the original pattern larger than the critical value is selected. In contrast, for the phase shift mask curve, the portion with the critical dimension of the original pattern smaller than the critical value is selected. These two portions are combined as an optical characteristic curve. The mixed mode photomask can thus be fabricated according to the optical characteristic curve.Type: ApplicationFiled: January 23, 2002Publication date: May 30, 2002Inventors: Chin-Lung Lin, Yao-Ching Ku
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Patent number: 6291112Abstract: A method of automatically forming a rim PSM is provided. A first pattern comprising a conventional original pattern as a blinding layer and assist features around the conventional circuit pattern is designed. A portion of a Cr film and a portion of a phase shifting layer under the Cr film are removed with the first pattern. The removed portion of the Cr film and the removed portion of the phase shifting layer are positioned on the assist feature. A second pattern comprising the conventional circuit pattern and a half of the assist features is designed. A portion of the Cr film in positions other than on the second pattern is removed. The convention circuit pattern formed at the mask medium is defined as the blinding layer. The area of the assist features only comprise a quartz substrate that light can pass through. The other areas of the mask medium wherein the phase shifting layer remains is defined as the phase-shifting portion of the PSM.Type: GrantFiled: November 13, 1998Date of Patent: September 18, 2001Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Yao-Ching Ku
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Patent number: 6251564Abstract: A method for forming a pattern with both a logic-type and, a memory-type circuit is disclosed. The method includes first providing a wafer which includes a photoresist layer, then covering the photoresist layer with a first mask including an opaque area and a first pattern area. Forming a first pattern on the photoresist layer by a first exposure. Covering the photoresist layer with a second mask after the first mask is removed. Moreover, a second pattern is printed on the photoresist layer by a second exposure. Finally, the second mask is removed. The double-exposure method will enhance the resolution of the pattern defined on the photoresist layer.Type: GrantFiled: May 17, 1999Date of Patent: June 26, 2001Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Yao-Ching Ku
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Publication number: 20010003026Abstract: A method of manufacturing a strong PSM. A phase shifting layer is formed on a mask substrate, and a first opening and a second opening are formed within the phase shifting layer by patterning to expose a portion of the mask substrate. Thereafter, the mask substrate is etched along the first opening to a first depth wherein the first depth has a phase shift of 90° with the second opening. The mask substrate is etched again along the first opening to a second depth wherein the second depth has a phase shift of 180° with the second opening. An etching step is then carried out along the first opening and the second opening to obtain simultaneously a third depth and a fourth depth of the first opening and the second opening, respectively, with a phase shift of 180°.Type: ApplicationFiled: March 25, 1999Publication date: June 7, 2001Inventors: CHIN-LUNG LIN, YAO-CHING KU
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Patent number: 6165693Abstract: For a dense-line mask pattern, if the ratio of space width to line width is larger than 2.0 and the size of the line width is less than the exposure wave length, or for an iso-line mask pattern, if the size of the line width is less than the exposure wave length, assist features should be added and OAI should be used to increase the process window. For a dense-line mask pattern, if the ratio of space width to line width is smaller than 2.0, or for an iso-line mask pattern, if the size of the line width is larger than the exposure wavelength, no assist feature should be added.Type: GrantFiled: August 17, 1998Date of Patent: December 26, 2000Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Yao-Ching Ku
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Patent number: 6087049Abstract: A method of optical proximity correction suitable for use in a mixed mode photomask. An original pattern is to be -transferred from the mixed mode photomask. A binary mask curve and a phase shift mask curve reflecting relationship between critical dimensions of the photomask and the original pattern are obtained. A critical value of the critical dimension is selected. For the binary mask curve, the portion with the critical dimension of the original pattern larger than the critical value is selected. In contrast, for the phase shift mask curve, the portion with the critical dimension of the original pattern smaller than the critical value is selected. These two portions are combined as an optical characteristic curve. The mixed mode photomask can thus be fabricated according to the optical characteristic curve.Type: GrantFiled: December 7, 1999Date of Patent: July 11, 2000Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Yao-Ching Ku
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Patent number: 6064485Abstract: A method of optical proximity correction suitable for use in a mixed mode photomask. An original pattern is to be transferred from the mixed mode photomask. A binary mask curve and a phase shift mask curve reflecting relationship between critical dimensions of the photomask and the original pattern are obtained. A critical value of the critical dimension is selected. For the binary mask curve, the portion with the critical dimension of the original pattern larger than the critical value is selected. In contrast, for the phase shift mask curve, the portion with the critical dimension of the original pattern smaller than the critical value is selected. These two portions are combined as an optical characteristic curve. The mixed mode photomask can thus be fabricated according to the optical characteristic curve.Type: GrantFiled: June 30, 1999Date of Patent: May 16, 2000Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Yao-Ching Ku
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Patent number: 6016201Abstract: An inspection method for a correction pattern includes the following steps. An optical proximity correction is performed to an original pattern to obtain an optical proximity correction pattern. An "exclusive or" logic operation is done to the original pattern and the optical correction pattern to obtain an inspection pattern. The inspection pattern includes a number of kinds of line width sizing. The line width sizing of the inspection pattern is then compared with an optical correction reference size.Type: GrantFiled: August 17, 1998Date of Patent: January 18, 2000Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Yao-Ching Ku
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Patent number: 6013397Abstract: A method for automatically forming a sub-resolution PSM is provided. The shielding layer is designed by adding an assist feature to a peripheral region of an original shielding layer formed on a quartz substrate. Using an etching process with a etching mask, a portion of the original shielding layer is removed to form an original pattern and an assist feature. The assist feature is separated from the original pattern by a distance. A photoresist layer is tormed on the rim of the shielding layer so that the original pattern, half of the assist feature, and an exposed portion of the quartz substrate between the original pattern and the assist feature are exposed. A selective etching process is performed to etch the exposed portion of the quartz substrate to a certain depth so that it behaves like a phase shifting layer. After removing the photoresist layer, the sub-resolution PSM including the integrated circuit pattern and the assist feature is complete.Type: GrantFiled: November 4, 1998Date of Patent: January 11, 2000Assignee: United Microelectronics Corp.Inventors: Chin-Lung Lin, Yao-Ching Ku