Abstract: A semiconductor package having an optical device and a method of making the same, the package including a chip, an upper metal redistribution layer, a transparent insulating layer, and a lower metal redistribution layer. The chip has an active surface, a back surface, at least one through hole, an optical device, and at least one upper pad. The optical device is electrically connected to the upper pad. The through hole is filled with a metal post. An insulating layer is between the through hole wall and the metal post. The upper metal redistribution layer is on the chip active surface, and connects the upper pad and the metal post. The transparent insulating layer is on the active surface. The lower metal redistribution layer is on the back surface of the chip, and is connected to the metal post. A simplified manufacturing process having reduced cost is provided.

Abstract: The present invention relates to a semiconductor package having an optical device and a method of making the same. The package comprises a chip, an upper metal redistribution layer, a transparent insulating layer, and a lower metal redistribution layer. The chip has an active surface, a back surface, at least one through hole, an optical device, and at least one upper pad, wherein the optical device is electrically connected to the upper pad, and the through hole is filled with a metal post. An insulating layer is disposed between the wall of the through hole and the metal post. The upper metal redistribution layer is disposed on the active surface of the chip, and is used for connecting the upper pad and the metal post. The transparent insulating layer is disposed on the active surface of the wafer. The lower metal redistribution layer is disposed on the back surface of the chip, and is connected to the metal post.

Abstract: A process for testing IC wafer is disclosed. Prior to electrically testing chips on a wafer, the wafer is pre-cut to form a plurality of grooves aligned with the scribe lines on the active surface of the wafer. A step of singulating the wafer is performed to form a plurality of individual chips after completing electrical or reliability test of the chips. Due to the pre-cutting step the chips are still integrated on the wafer for accurately probing and testing. And the testing step can obtain the influence of defects between the test terminals and a UBM layer on the function of the chips.

Abstract: A manufacturing method of a semiconductor wafer package mainly comprises the following steps. Firstly, a semiconductor wafer having a plurality of bonding pads and a passivation layer exposing the bonding pads is provided. Next, under bump metallurgy layers are formed on each of the bonding pads respectively. Then, a mask is formed above the semiconductor wafer to expose the under bump metallurgy layers through each of the openings of the mask. Afterwards, a plurality of bump structures are disposed separately in the openings wherein each of the bump structures has a bump and a reinforced layer covering the bump. Finally, a reflow step is performed so that each of the reflowed bumps is connected to the corresponding under bump metallurgy layer and the reinforced layers are transformed into bump-reinforced collars to cover the under bump metallurgy layers and encompass the bumps. In addition, a semiconductor wafer package, which is formed by the manufacturing method, is provided.

Abstract: A manufacturing method of a semiconductor wafer package mainly comprises the following steps. Firstly, a semiconductor wafer having a plurality of bonding pads and a passivation layer exposing the bonding pads is provided. Next, under bump metallurgy layers are formed on each of the bonding pads respectively. Then, a mask is formed above the semiconductor wafer to expose the under bump metallurgy layers through each of the openings of the mask. Afterwards, a plurality of bump structures are disposed separately in the openings wherein each of the bump structures has a bump and a reinforced layer covering the bump. Finally, a reflow step is performed so that each of the reflowed bumps is connected to the corresponding under bump metallurgy layer and the reinforced layers are transformed into bump-reinforced collars to cover the under bump metallurgy layers and encompass the bumps. In addition, a semiconductor wafer package, which is formed by the manufacturing method, is provided.

Abstract: A method of dicing a wafer is disclosed. A wafer with an active surface and a back surface is provided. Prior to dicing the wafer, a removable layer is formed on the back surface of the wafer. The removable layer is attached to a tape, such as a sawing tape. After the wafer is singulated and the adhesion of the removable layer is reduced or removed, the separate chips singulated from the wafer are easily removed from the tape. Because of the removable layer attached on the back surface of the wafer, the cutting stress caused by singulating the wafer will be transferred without concentrated at the back surface of the wafer so as to prevent the wafer from chipping and being warped.

Abstract: The present invention relates to a semiconductor package having an optical device and a method of making the same. The package comprises a chip, an upper metal redistribution layer, a transparent insulating layer, and a lower metal redistribution layer. The chip has an active surface, a back surface, at least one through hole, an optical device, and at least one upper pad, wherein the optical device is electrically connected to the upper pad, and the through hole is filled with a metal post. An insulating layer is disposed between the wall of the through hole and the metal post. The upper metal redistribution layer is disposed on the active surface of the chip, and is used for connecting the upper pad and the metal post. The transparent insulating layer is disposed on the active surface of the wafer. The lower metal redistribution layer is disposed on the back surface of the chip, and is connected to the metal post.

Abstract: A method of dicing a wafer is disclosed. A wafer with an active surface and a back surface is provided. Prior to dicing the wafer, a removable layer is formed on the back surface of the wafer. The removable layer is attached to a tape, such as a sawing tape. After the wafer is singulated and the adhesion of the removable layer is reduced or removed, the separate chips singulated from the wafer are easily removed from the tape. Because of the removable layer attached on the back surface of the wafer, the cutting stress caused by singulating the wafer will be transferred without concentrated at the back surface of the wafer so as to prevent the wafer from chipping and being warped.

Abstract: A process for testing IC wafer is disclosed. Prior to electrically testing chips on a wafer, the wafer is pre-cut to form a plurality of grooves aligned with the scribe lines on the active surface of the wafer. A step of singulating the wafer is performed to form a plurality of individual chips after completing electrical or reliability test of the chips. Due to the pre-cutting step the chips are still integrated on the wafer for accurately probing and testing.

Abstract: A manufacturing method of a semiconductor wafer package mainly comprises the following steps. Firstly, a semiconductor wafer having a plurality of bonding pads and a passivation layer exposing the bonding pads is provided. Next, under bump metallurgy layers are formed on each of the bonding pads respectively. Then, a mask is formed above the semiconductor wafer to expose the under bump metallurgy layers through each of the openings of the mask. Afterwards, a plurality of bump structures are disposed separately in the openings wherein each of the bump structures has a bump and a reinforced layer covering the bump. Finally, a reflow step is performed so that each of the reflowed bumps is connected to the corresponding under bump metallurgy layer and the reinforced layers are transformed into bump-reinforced collars to cover the under bump metallurgy layers and encompass the bumps. In addition, a semiconductor wafer package, which is formed by the manufacturing method, is provided.

Abstract: A semiconductor wafer includes a plurality of areas and an array of dice disposed within each of the areas. The feature of the present invention is that at least two fiducial marks are disposed in each of the areas. The present invention further provides a method of testing a sawed semiconductor wafer.

Abstract: A semiconductor package includes a substrate, a chip and a marking film. The semiconductor chip is electrically connected to the substrate. A marking film is formed on the back surface of the chip. Thereby, a mark is formed by patterning the marking film. Generally, the marking film is a dry film or a tape. Not only the marking film prevents the singulated chips from being in a fry-chip manner but also can be patterned by laser ablation instead of the conventional method of forming a mark directly on the back surface of the chip. Accordingly, the chip will be prevented from destroying in the duration of performing the marking process.

Abstract: A semiconductor wafer includes a plurality of areas and an array of dice disposed within each of the areas. The feature of the present invention is that at least two fiducial marks are disposed in each of the areas. The present invention further provides a method of testing a sawed semiconductor wafer.

Abstract: In a cavity down BGA packaging structure, a circuit substrate is bonded onto a heat spreader. A cavity formed is formed in the circuit substrate into which a chip is bonded onto the heat spreader. The circuit substrate has at least an insulating layer, a patterned wiring layer, and a via electrically connected to the heat spreader. A first ground pad, ball pad, and first contact pad are defined on the patterned wiring layer, wherein the first ground pad is spaced apart from and electrically connected to the via. The chip comprises at least a second contact pad and a second ground pad respectively connected to the first contact pad and the heat spreader. An encapsulant material encapsulates the cavity, the chip, and the first and second contact pads. A plurality of solder balls are attached to the first ground pad and ball pad.

Abstract: A heat-spread substrate consisting of a metal heat spreader and a substrate is disclosed. The metal heat spreader has a surface with a cavity, which is adapted for supporting a die. Such surface further includes a ground ring arranged at the periphery of the cavity; a substrate-supporting surface surrounding the periphery of the ground ring; a plurality of first ground pads arranged at the periphery of the substrate-supporting surface; and a plurality of second ground pads arranged on the substrate-supporting surface and protruding it. The substrate is provided on the substrate-supporting surface having a plurality of through holes. The through holes corresponds to the first ground pad so as to make it be located therein, respectively. The substrate further includes a plurality of mounting pads and a plurality of ball pads, in which the mounting pads are close to the cavity, and the first ground pad, the second ground pads and the ball pads are formed in the form of ball grid array and are coplanar roughly.

Abstract: A laser method for forming vias comprises: providing a heat sink; locally oxidizing a surface of the heat sink into a copper oxide film; bonding a substrate onto the heat sink at the copper oxide layer locations, wherein the substrate comprises at least a patterned trace layer and an insulating layer to which is bonded the heat sink, the insulating layer comprising a plurality of through holes that expose the portions of the copper oxide film; removing the copper oxide exposed through the through holes by laser beam; disposing a plurality of solder balls respectively in the through holes; and reflowing the solder balls to form a plurality of vias.

Abstract: A press plate mainly includes a plate and a probe. The plate has an opening which corresponds to a chip of the substrate and inner finger thereof, and the probe is elastically attached to the edge of the opening for wire bond checking. After the wire bonding process, the wire connecting the chip and the inner finger of the substrate and the probe of the wire bond checking system form a loop. Then a current is sent to the substrate from the wire bond checking system to check for the occurrence of wire occurring lift bond or missing wire.

Abstract: A base mainly includes a heating plate and a probe. The probe is attached to the surface of a heating plate which serves to place a substrate having an ball pad on a lower surface facing the probe of the heating plate. The probe contacts the ball pad of the lower surface of the substrate to form a closed loop for wire bond checking while the substrate is placed on the heating plate. When processing the wire bond, the wire connecting the chip and the ball pad of the substrate and the probe connecting to the wire bond checking system form a loop. Then a current is sent to the substrate from the wire bond checking system to check for wire lift bond or missed wire. When the wire bond checking system finds an occurrence of lift bond or missing wire, the wire bonding process stops immediately to avoid unnecessary wire bonding.