Semiconductor wafer package and manufacturing method thereof
A manufacturing method of a semiconductor wafer package mainly comprises the following steps. Firstly, a semiconductor wafer having a plurality of bonding pads and a passivation layer exposing the bonding pads is provided. Next, under bump metallurgy layers are formed on each of the bonding pads respectively. Then, a mask is formed above the semiconductor wafer to expose the under bump metallurgy layers through each of the openings of the mask. Afterwards, a plurality of bump structures are disposed separately in the openings wherein each of the bump structures has a bump and a reinforced layer covering the bump. Finally, a reflow step is performed so that each of the reflowed bumps is connected to the corresponding under bump metallurgy layer and the reinforced layers are transformed into bump-reinforced collars to cover the under bump metallurgy layers and encompass the bumps. In addition, a semiconductor wafer package, which is formed by the manufacturing method, is provided.
Latest Advanced Semiconductor Engineering, Inc. Patents:
1. Field of Invention
This invention relates to a semiconductor wafer package. More particularly, the present invention is related to a semiconductor wafer package having a plurality of solder bumps encompassed by a plurality of bump-reinforced collars respectively and the manufacturing method thereof.
2. Related Art
In this information explosion age, integrated circuits products are used almost everywhere in our daily life. As fabricating technique continue to improve, electronic products having powerful functions, personalized performance and a higher degree of complexity are produced. Nowadays, most electronic products are relatively light and have a compact body. Hence, in semiconductor production, various types of high-density semiconductor packages, for example ball grid array package (BGA), chip-scale package (CSP), multi-chips module package (MCM) and flip chip package (F/C), have been developed.
However, as mentioned above, flip chip is one of the most commonly used techniques for forming an integrated circuits package. Compared with a wire-bonding package or a tape automated bonding (TAB) package, a flip-chip package has a shorter electrical path on average and has a better overall electrical performance. In said flip-chip package, the bonding pads on a chip and the contacts on a substrate are connected together through a plurality of bumps formed by the method of bumping process. It should be noted that there is further an under bump metallurgy layer disposed on the bonding pads of the chip to be regarded as a connection medium for connecting to the bumps and enhancing the mechanical strength of the connection of the chip to the substrate after said chip is attached to the substrate.
Moreover, said manufacturing method of a semiconductor wafer package is usually utilized in flip chip technology. Therein, a plurality of under bump metallurgy layers are formed on the corresponding bonding pads of the wafer respectively, and a plurality of solder balls or bumps are mounted onto the under bump metallurgy layers so as to be regarded as interconnections for electrically and mechanically connecting the chip and the substrate when the chip is flip-chip bonded to the substrate.
Referring to
Next, referring to
In general, each of the under bump metallurgy layers 106 mainly comprises an adhesive layer, a barrier layer and a wetting layer. The adhesive layer is utilized to enhance the mechanical strength of the connection of the bonding pad 102 to the barrier layer, wherein the material of the adhesive layer is made of aluminum or titanium. The barrier layer is utilized to avoid the diffusion of the underlying metal, wherein the material of the barrier layer usually includes nickel-vanadium alloy, nickel-copper alloy and nickel. In addition, the wetting layer, for example a copper layer, is utilized to enhance the wettability of the solder bump 109 with the under bump metallurgy layer 106. It should be noted that the under bump metallurgy layers 106 are formed through the processes of placing photo-resist, proceeding plating or sputtering metal on the surface of the semiconductor wafer 100 and etching the metal.
As mentioned above, there is needed the bump-reinforced collar 112 with a thickness not less than first-six of the diameter or the height of the reflowed solder bump 110 to well cover the reflowed solder bump 110 and enhance the mechanical reliability of the reflowed solder bump 110. To be noted, each of the reinforced layers 108 is disposed on the corresponding bonding pad 102 through printing process by using photo-mask and stencil, accordingly, said reinforced layer 108 is not well and equally distributed on the under bump metallurgy layer 106. Moreover, the solder bumps 109 are directly placed on the reinforced layers 108 before the bumps 109 are reflowed; and then the reinforced layers 108 are melted to be transformed into bump-reinforced collars 112 to partially cover and encompass the reflowed solder bumps 110 to have the reflowed solder bumps 110 securely attached to the under bump metallurgy layers 106 by penetrating the reinforced layers 108 after reflowing the solder bumps 110. Thus, the portion of each of the reflowed solder bumps 110 not covered by the bump-reinforced collar 112 is not substantially the same with each other. Namely, the height of each reflowed solder bump 110 encompassed by the reinforced collar 112 is not substantially the same with each other, for example H1 is different from H2 as shown in
Per the above disadvantages, it will lower the mechanical reliability of the semiconductor wafer package and the combination of said chip of the semiconductor wafer package and substrate. Therefore, providing another method for forming bumps to solve the mentioned-above disadvantages is the most important task in this invention.
SUMMARY OF THE INVENTIONIn view of the above-mentioned problems, this invention is to provide a semiconductor wafer package having a plurality of reflowed bumps which are covered by the bump-reinforced collars respectively and the manufacturing method thereof.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a manufacturing method of a semiconductor wafer package mainly comprising the following steps. Firstly, a semiconductor wafer is provided, wherein the semiconductor wafer has a plurality of bonding pads, a plurality of under bump metallurgy layers and a passivation layer exposing the under bump metallurgy layers located over the bonding pads. Next, a mask, such as a photo-resist layer or a photo-mask, is provided to cover the active surface of the semiconductor wafer and form a plurality of openings to expose the under bump metallurgy layers located over the bonding pads. Afterwards, a plurality of solder-bump structures are placed in the openings. To be noted, each solder-bump structure comprises a solder bump and a reinforced layer covering the solder bump. Finally, a reflow process is performed to melt the solder-bump structures to have the solder bumps transformed into reflowed solder bumps and attached to the under bump metallurgy layers and have the reinforced layer transformed into bump-reinforced collars to cover the reflowed solder bumps and the under bump metallurgy layers. And then the mask is removed to complete the semiconductor wafer package process to form a semiconductor wafer package.
Moreover, the invention also provides a semiconductor wafer package according to the above manufacturing method. Therein, the semiconductor wafer package mainly comprises a semiconductor wafer, a plurality of reflowed solder bumps disposed on the semiconductor wafer and a plurality of bump-reinforced collars covering the reflowed solder bumps, respectively, to at least expose the top of the reflowed solder bumps. Said semiconductor wafer has an active surface, a passivation layer located on the active surface, a plurality of bonding pads exposed out of the passiveation layer and a plurality of under bump metallurgy layers disposed on the bonding pads. In addition, the height of the portion of each reflowed solder bump not covered by the bump-reinforced collar is substantially the same with each other.
As mentioned above, the reinforced layer formed on and covering each solder bump to form a solder-bump structure is a thin reinforced layer, and said reinforced layer is well and equally distributed on each solder bump. Accordingly, when the solder-bump structures are reflowed to have the reinforced layer melted, there will be no melted reinforced layer disposed on the under bump metallurgy layers so as to easily transform the reinforced layer into a plurality of bump-reinforced collars to well cover the reflowed solder bumps. Thus, the height of the portion of each reflowed solder bump covered by the bump-reinforced collar 210 is substantially the same with each other, for example H3 and H4 as shown in
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
BRIEF DESCRIPTION OF THE DRAWINGSThe invention will become more fully understood from the detailed description given herein below illustrations only, and thus are not limitative of the present invention, and wherein:
FIGS. 4 to 7 are partially enlarged cross-sectional views showing the progression of steps for forming a semiconductor wafer package according to the preferred embodiment of this invention.
DETAILED DESCRIPTION OF THE INVENTIONThe semiconductor wafer package according to the preferred embodiment of this invention will be described herein below with reference to the accompanying drawings, wherein the same reference numbers are used in the drawings and the description to refer to the same or like parts.
Referring to
Besides, each of the under bump metallurgy layers 206 generally comprises an adhesive layer, a barrier layer and a wetting layer. The adhesive layer is utilized to enhance the mechanical strength of the connection of the bonding pad 202 to the barrier layer, wherein the material of the adhesive layer is made of aluminum or titanium. The barrier layer is utilized to avoid the diffusion of the underlying metal, wherein the material of the barrier layer usually includes nickel-vanadium alloy, nickel-copper alloy and nickel. In addition, the wetting layer, for example a copper layer, is utilized to enhance the wettability of the reflowed solder bump 208 with the under bump metallurgy layer 206. It should be noted that the under bump metallurgy layers 206 are formed through the processes of placing photo-resist, proceeding plating or sputtering metal on the surface of the semiconductor wafer 200 and etching the metal
Next, referring to the drawings shown from
Firstly, referring to
Next, referring to
As mentioned above, referring to
Besides, the reinforced layer 308b covering the surface of the solder bump 308a is thin so that that the reinforced layer 308b is distributed well and equally on the surface of the solder bump 308a. In such a manner, when the reinforced layer 308b is melted to be transformed into the bump-reinforced collar 310 to cover the relowed solder bump 309, the height of the portion of the reflowed solder bump 309 is substantially the same with the others. Namely, the heights of H5 and H6 as shown in
To be continued and as specified in the above, when the under bump metallurgy layer is extended over the passivation layer to be regarded as a redistributed layer and a redistributed pad, said above-mentioned method shall also apply to the semiconductor wafer having redistributed layers and redistributed pads.
As mentioned above, the reinforced layer formed on and covering each solder bump as a solder-bump structure is a thin reinforced layer and said reinforced layer is well and equally distributed on each solder bump. Accordingly, when the solder-bump structures are reflowed to have the reinforced layer melted, there will be no melted reinforced layer disposed on the under bump metallurgy layers so as to easily transform the reinforced layer into a plurality of bump-reinforced collars to well cover the reflowed solder bumps. Thus, the height of the portion of each solder bump covered by the reinforced layer is substantially the same with each other, after said reflow process is performed.
Although the invention has been described in considerable detail with reference to certain preferred embodiments, it will be appreciated and understood that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims
1-9. (canceled)
10. A semiconductor wafer package, comprising:
- a semiconductor wafer having an active surface, a plurality of bonding pads formed on the active surface, a passivation layer located above the semiconductor wafer and exposing the bonding pads and a plurality of under bump metallurgy layers formed on the bonding pads;
- a plurality of reflowed bumps disposed on the under bump metallurgy layers; and
- a plurality of bump-reinforced collars, the bump-reinforced collars encompassing the reflowed bumps and covering the under bump metallurgy layers, wherein each of the reflowed bumps is exposed out of the each bump-reinforced collar having an exposed portion with a height substantially the same with each other.
11. The semiconductor wafer package of claim 10, wherein the reflowed bump is a solder bump.
12. The semiconductor wafer package of claim 10, wherein the bump-reinforced collar is made of a polymer material.
13. The semiconductor wafer package of claim 10, wherein the passivation layer is made of a material selected from silicon nitride, phosphosilicate glass and silicon oxide.
14. The semiconductor wafer package of claim 10, wherein each of the under bump metallurgy layers comprises a titanium layer, a nickel-vanadium layer and a copper layer.
15. The semiconductor wafer package of claim 10, wherein the height of the exposed portion of the reflowed bump is at least equal to the first-six of the height of the reflowed bump.
16. The semiconductor wafer package of claim 10, wherein the height of the exposed portion of reflowed bumps is more than the first-six of the height of the reflowed bump.
17. The semiconductor wafer package of claim 10, wherein said each reflowed bump is a gold bump.
18. The semiconductor wafer package of claim 10, wherein each of the under bump metallurgy layers is made of a material selected from titanium, titanium-tungsten alloy, aluminum, aluminum-nickel, nickel-vanadium, chromium-copper alloy, copper and nickel-vanadium.
19. The semiconductor wafer package of claim 10, wherein the reflowed bumps are located over the bonding pads.
20. The semiconductor wafer package of claim 10, wherein one of the under bump metallurgy layers is extended over the active surface of the semiconductor wafer.
Type: Application
Filed: Aug 24, 2006
Publication Date: Dec 21, 2006
Applicant: Advanced Semiconductor Engineering, Inc. (Kaoshiung)
Inventor: Yao-Hsin Feng (Hualien City)
Application Number: 11/508,896
International Classification: H01L 21/44 (20060101);