Abstract: An IC device includes a first anti-fuse structure including a first dielectric layer between a first gate conductor and a first active area, and a second anti-fuse structure including a second dielectric layer between a second gate conductor and the first active area. A first via is electrically connected to the first gate conductor at a first location a first distance from the first active area, a second via is electrically connected to the second gate conductor at a second location a second distance from the first active area, and the first distance is approximately equal to the second distance.

Abstract: An IC structure includes a first active area including a first plurality of fin structures extending in a first direction, a second active area including a second plurality of fin structures extending in the first direction, an electrical fuse (eFuse) extending in the first direction between the first and second active areas and electrically connected to each of the first and second pluralities of fin structures, a first plurality of gate structures extending over the first active area perpendicular to the first direction, a second plurality of gate structures extending over the second active area in the second direction, a first signal line extending in the first direction adjacent to the first active area and electrically connected to the first plurality of gate structures, and a second signal line extending in the first direction adjacent to the second active area and electrically connected to the second plurality of gate structures.

Abstract: A semiconductor device includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Abstract: A method includes: coupling a first gate to a first word line through a first gate via, wherein the first gate extends along a first direction; coupling the first gate to a second word line through a second gate via, wherein each of the first gate, a second gate, the first gate via and the second gate via is disposed on a first active area which extends along the second direction, wherein the second gate extends along the first direction and is separated from the first gate along a second direction; coupling the first active area to a first bit line through a first conductive via; and aligning the first gate via, the second gate via and the a first conductive via with each other along the second direction.

Abstract: An integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer and coupled between the transistor and a first data line. The second fuse element is formed in the second conductive layer and coupled between the transistor and a second data line. The first fuse element and the second fuse element are disposed at a same side of the transistor.

Abstract: An IC device includes an active area positioned in a substrate, first and second contact structures overlying and electrically connected to the active area, a conductive element overlying and electrically connected to each of the first and second contact structures, an anti-fuse transistor device including a dielectric layer between a gate structure and the active area, a first selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the first contact structure, and a second selection transistor overlying the active area adjacent to each of the anti-fuse transistor device and the second contact structure.

Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, a first gate electrode and a second gate electrode over the substrate and extending in a second direction, the semiconductor fin extending through the second gate electrode and terminating on the first gate electrode at one end of the semiconductor fin, and a first gate spacer and a second gate spacer laterally surrounding the first gate electrode and the second gate electrode, respectively. The one end of the semiconductor fin is surrounded by the first gate electrode. The first gate spacer includes a top substantially at a same height of a top of the second gate spacer.

Abstract: An IC structure includes a bit line extending in a first direction, first and second pluralities of FinFETs, and a plurality of eFuses. The FinFETs of the first plurality of FinFETs alternate with the FinFETs of the second plurality of FinFETs along the bit line, each eFuse of the plurality of eFuses includes a conductive segment extending between first and second contact regions, the first contact region is electrically connected to the bit line, and the second contact region is electrically connected to each of an adjacent FinFET of the first plurality of FinFETs and an adjacent FinFET of the second plurality of FinFETs.

Abstract: A structure includes anti-fuse cells. The anti-fuse cells include a first active area, a first gate, a second gate, at least one first gate via, and at least one second gate via. The first gate and the second gate are separate from each other. The first gate and the second gate extend to cross over the first active area. The at least one first gate via is coupled to the first gate and disposed directly above the first active area. The at least one second gate via is coupled to the second gate. The first gate is coupled through the at least one first gate via to a first word line for receiving a first programming voltage, and the second gate is coupled through the at least one second gate via to a second word line for receiving a first reading voltage.

Abstract: An integrated circuit includes a front-side horizontal conducting line in a first metal layer, a front-side vertical conducting line in a second metal layer, a front-side fuse element, and a backside conducting line. The front-side horizontal conducting line is directly connected to the drain terminal-conductor of a transistor through a front-side terminal via-connector. The front-side vertical conducting line is directly connected to the front-side horizontal conducting line through a front-side metal-to-metal via-connector. The front-side fuse element having a first fuse terminal conductively connected to the front-side vertical conducting line. The backside conducting line is directly connected to the source terminal-conductor of the transistor through a backside terminal via-connector.

Abstract: In one aspect of the present disclosure, a semiconductor device is disclosed. In some embodiments, the semiconductor device includes a first conductive structure extending in a first direction, the first conductive structure coupled to a metal-oxide-semiconductor (MOS) device; a second conductive structure extending in the first direction and spaced from the first conductive structure in a second direction perpendicular to the first direction; a dielectric material extending in the second direction and disposed over, in a third direction perpendicular to the first direction and the second direction, the first conductive structure; and a via structure disposed over the second conductive structure and in contact with the dielectric material, wherein the dielectric material is configured to create a channel between the first conductive structure and the via structure when a voltage is applied to the second conductive structure.

Abstract: A one-time programmable (OTP) bit cell includes a substrate including a front side and a back side, an active area on the front side, a first read transistor including a first gate and a first portion of the active area intersected by the first gate, a program transistor including a second gate and a second portion of the active area intersected by the second gate, a first electrical connection to the first gate, a second electrical connection to the second gate, and a third electrical connection to the active area. At least one of the first, second, or third electrical connections includes a metal line positioned on the back side.

Abstract: A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.

Abstract: An integrated circuit is disclosed. The integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer disposed above the first conductive layer. The second fuse element is formed in the second conductive layer and is coupled to the first fuse element. The transistor is coupled through the first fuse element to a first data line for receiving a first data signal, and the transistor is coupled through the second fuse element to a second data line for receiving a second data signal. A method of fabricating an integrated circuit (IC) is also disclosed herein.

Abstract: A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode at one end. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode. The one end of the semiconductor fin is surrounded by the first gate electrode.

Abstract: An integrated circuit (IC) device includes a first active region extending along a first direction, a first pair of gate regions extending across the first active region along a second direction transverse to the first direction, and a first metal layer. The first pair of gate regions and the first active region configure a first program transistor and a first read transistor sharing a common source/drain region. The first metal layer includes a first program word line pattern over and coupled to the gate region of the first program transistor, a first read word line pattern over and coupled to the gate region of the first read transistor, a first source line pattern coupled to another source/drain region of the first program transistor, and a first bit line pattern coupled to another source/drain region of the first read transistor.

Abstract: An integrated circuit (IC) device includes transistor and programmable structure regions. The transistor region includes a source structure configured to receive a reference voltage, a first portion of a drain structure, and a gate electrode positioned between the source structure and the first portion of the drain structure, and configured to receive an activation signal. The programmable structure region includes a second portion of the drain structure, a first signal line configured to receive an operational voltage, a second signal line, a gate via underlying and electrically connected to the first signal line, and a drain via positioned between and electrically connected to the second portion of the drain structure and the second signal line. Portions of the first signal line including a gate via location and the second signal line including a drain via location are positioned in parallel in a same metal layer of the IC device.

Abstract: A structure includes a word line, a bit line, and an anti-fuse cell. The anti-fuse cell includes a reading device, a programming device, and a dummy device. The reading device includes a first gate coupled to the first word line, a first source/drain region coupled to the bit line, and a second source/drain region. The first source/drain region and the second source/drain region are on opposite sides of the first gate. The programming device includes a second gate, a third source/drain region coupled to the second source/drain region, and a fourth source/drain region. The third source/drain region and the fourth source/drain region are on opposite sides of the second gate. The dummy device includes a third gate, a fifth source/drain region coupled to the fourth source/drain region, and a sixth source/drain region. The fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate.

Abstract: A memory device includes at least one bit line, at least one source line, at least one program word line, at least one read word line, and at least one memory cell including a program transistor and a read transistor. The program transistor includes a gate terminal coupled to the at least one program word line, a first terminal coupled to the at least one source line, and a second terminal. The read transistor includes a gate terminal coupled to at least one read word line, a first terminal coupled to the at least one bit line, and a second terminal coupled to the second terminal of the program transistor.

Abstract: An antifuse structure and IC devices incorporating such antifuse structures in which the antifuse structure includes an dielectric antifuse structure formed on an active area having a first dielectric antifuse electrode, a second dielectric antifuse electrode extending parallel to the first dielectric antifuse electrode, a first dielectric composition between the first dielectric antifuse electrode and the second dielectric antifuse electrode, and a first programming transistor electrically connected to a first voltage supply wherein, during a programming operation a programming voltage is selectively applied to certain of the dielectric antifuse structures to form a resistive direct electrical connection between the first dielectric antifuse electrode and the second dielectric antifuse electrode.