Patents by Inventor Yao-Jen Yang

Yao-Jen Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190287900
    Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.
    Type: Application
    Filed: November 28, 2018
    Publication date: September 19, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Sheng Chang, Shao-Tung Peng, Shao-Yu Chou, Liang Chuan Chang, Yao-Jen Yang
  • Publication number: 20190251223
    Abstract: A method of generating an IC layout diagram includes intersecting an active region with first and second gate regions to define locations of first and second anti-fuse structures, overlying the first gate region with a first conductive region to define a location of an electrical connection between the first conductive region and first gate region, and overlying the second gate region with a second conductive region to define a location of an electrical connection between the second conductive region and second gate region. The first and second conductive regions are aligned along a direction perpendicular to a direction along which the first and second gate regions extend, and at least one of intersecting the active region with the first gate region, intersecting the active region with the second gate region, overlying the first gate region, or overlying the second gate region is executed by a processor of a computer.
    Type: Application
    Filed: January 18, 2019
    Publication date: August 15, 2019
    Inventors: Meng-Sheng Chang, Chen-Ming Hung, Shao-Yu Chou, Yao-Jen Yang
  • Patent number: 10163783
    Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Sheng Chang, Shao-Tung Peng, Shao-Yu Chou, Liang Chuan Chang, Yao-Jen Yang