Patents by Inventor Yao Ko
Yao Ko has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150132905Abstract: The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.Type: ApplicationFiled: November 17, 2014Publication date: May 14, 2015Inventors: Ta-Chuan Liao, Chien-Kuo Yang, Felix Ying-Kit Tsui, Shih-Hsien Chen, Liang-Tai Kuo, Chun-Yao Ko
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Patent number: 9021099Abstract: System and method for load balancing multiple file transfer protocol (FTP) servers to service secure FTP sessions having encrypted signals are disclosed. In one aspect, embodiments of the system include multiple FTP servers coupled to a load balancing agent. Each of the multiple FTP servers is associated with a unique port range and the load balancer receives an encrypted data signal in a secure FTP session on a given port and uses a port range within which the given port falls to identify which of the multiple FTP servers a corresponding control signal of the secure FTP session was previously sent.Type: GrantFiled: August 2, 2012Date of Patent: April 28, 2015Assignee: Box, Inc.Inventor: Yao Ko
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Publication number: 20150098266Abstract: Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hsien CHEN, Hau-Yan LU, Liang-Tai KUO, Chun-Yao KO, Felix Ying-Kit TSUI
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Patent number: 8962439Abstract: A method of programming a memory cell includes causing a current to flow through a first silicide-containing portion and a second silicide-containing portion of the memory cell; and causing, by the current, an electron-migration effect to form an extended silicide-containing portion within the gap such that the memory cell is converted from a first state into a second state. The memory cell includes a silicon-containing line continuously extending between a first region and a second region; the first silicide-containing portion over the silicon-containing line and adjacent to the first region; and the second silicide-containing portion over the silicon-containing line and adjacent to the second region. The first silicide-containing portion and the second silicide-containing portion are separated by a gap if the memory cell is at the first state. The extended silicide-containing portion extends from the second silicide-containing portion towards the first silicide-containing portion.Type: GrantFiled: June 11, 2014Date of Patent: February 24, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyun-Ying Lin, Chun-Yao Ko, Ting-Chen Hsu
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Patent number: 8952442Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.Type: GrantFiled: June 26, 2014Date of Patent: February 10, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hung Fu, Chun-Yao Ko, Tuo-Hsin Chien, Ting-Chen Hsu
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Publication number: 20150016180Abstract: Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate.Type: ApplicationFiled: September 29, 2014Publication date: January 15, 2015Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20140357137Abstract: A contact cage includes a sheet member having a plurality of first elongated slots and a plurality of second elongated slots respectively linearly arranged on the sheet member. A protruding portion is respectively defined between each two adjacent first elongated slots and each two adjacent second elongated slots and it is bent to provide at least one end point. Thus, the contact cage can be rolled up in a configuration of a hollow cylinder and positioned within a female terminal, enabling the end points to provide a larger contact area and to prolong the service life of the female terminal.Type: ApplicationFiled: August 19, 2013Publication date: December 4, 2014Applicant: K. S. TERMINALS INC.Inventors: Sheng-Sian SIAN, Tung-Yao KO
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Publication number: 20140346655Abstract: A method of programming a memory cell includes causing a current to flow through a first silicide-containing portion and a second silicide-containing portion of the memory cell; and causing, by the current, an electron-migration effect to form an extended silicide-containing portion within the gap such that the memory cell is converted from a first state into a second state. The memory cell includes a silicon-containing line continuously extending between a first region and a second region; the first silicide-containing portion over the silicon-containing line and adjacent to the first region; and the second silicide-containing portion over the silicon-containing line and adjacent to the second region. The first silicide-containing portion and the second silicide-containing portion are separated by a gap if the memory cell is at the first state. The extended silicide-containing portion extends from the second silicide-containing portion towards the first silicide-containing portion.Type: ApplicationFiled: June 11, 2014Publication date: November 27, 2014Inventors: Jyun-Ying LIN, Chun-Yao KO, Ting-Chen HSU
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Patent number: 8890225Abstract: The NVM device includes a semiconductor substrate having a first region and a second region. The NVM device includes a data-storing structure formed in the first region and designed operable to retain charges. The NVM device includes a capacitor formed in the second region and coupled with the data-storing structure for data operations. The data-storing structure includes a first doped well of a first-type in the semiconductor substrate. The data-storing structure includes a first gate dielectric feature on the first doped well. The data-storing structure includes a first gate electrode disposed on the first gate dielectric feature and configured to be floating. The capacitor includes a second doped well of the first-type. The capacitor includes a second gate dielectric feature on the second doped well. The capacitor also includes a second gate electrode disposed on the second gate dielectric feature and connected to the first gate electrode.Type: GrantFiled: October 14, 2011Date of Patent: November 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ta-Chuan Liao, Chien-Kao Yang, Ying-Kit Tsui, Shih-Hsien Chen, Liang-Tai Kuo, Chun-Yao Ko
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Publication number: 20140308798Abstract: A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.Type: ApplicationFiled: June 26, 2014Publication date: October 16, 2014Inventors: Ching-Hung Fu, Chun-Yao Ko, Tuo-Hsin Chien, Ting-Chen Hsu
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Patent number: 8853079Abstract: A method of forming a device includes forming a silicon-containing line continuously extending between a first node and a second node. A first silicide-containing portion and a second silicide-containing portion are formed over the silicon-containing line. The first silicide-containing portion is separated from the second silicide-containing portion by a predetermined distance, and the predetermined distance is substantially equal to or less than a length of the silicon-containing line.Type: GrantFiled: January 10, 2014Date of Patent: October 7, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyun-Ying Lin, Chun-Yao Ko, Ting-Chen Hsu
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Patent number: 8848428Abstract: One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.Type: GrantFiled: July 13, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Patent number: 8772854Abstract: A device includes an active region and a coupling capacitor. The capacitor includes a first floating gate as an upper capacitor plate of the coupling capacitor, and a doped semiconductor region as a lower capacitor plate of the coupling capacitor. The doped semiconductor region includes a surface portion at a surface of the active region, and a sidewall portion lower than a bottom surface of the surface portion. The sidewall portion is on a sidewall of the active region. A capacitor insulator is disposed between the upper capacitor plate and the lower capacitor plate. The capacitor insulator includes an upper portion, and a sidewall portion lower than a bottom surface of the upper portion.Type: GrantFiled: April 2, 2012Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Hung Fu, Chun-Yao Ko, Tuo-Hsin Chien, Ting-Chen Hsu
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Publication number: 20140167118Abstract: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; and an image sensor formed in the semiconductor layer.Type: ApplicationFiled: February 20, 2014Publication date: June 19, 2014Applicant: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Chung-Wei Chang, Han-Chi Liu, Chun-Yao Ko, Shou-Gwo Wuu
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Publication number: 20140124891Abstract: A method of forming a device includes forming a silicon-containing line continuously extending between a first node and a second node. A first silicide-containing portion and a second silicide-containing portion are formed over the silicon-containing line. The first silicide-containing portion is separated from the second silicide-containing portion by a predetermined distance, and the predetermined distance is substantially equal to or less than a length of the silicon-containing line.Type: ApplicationFiled: January 10, 2014Publication date: May 8, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jyun-Ying LIN, Chun-Yao KO, Ting-Chen HSU
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Patent number: 8719445Abstract: System and method for load balancing multiple file transfer protocol (FTP) servers to service secure FTP sessions having encrypted signals are disclosed. In one aspect, embodiments of the system include multiple FTP servers coupled to a load balancing agent. Each of the multiple FTP servers is associated with a unique port range and the load balancer receives an encrypted data signal in a secure FTP session on a given port and uses a port range within which the given port falls to identify which of the multiple FTP servers a corresponding control signal of the secure FTP session was previously sent.Type: GrantFiled: October 11, 2012Date of Patent: May 6, 2014Assignee: Box, Inc.Inventor: Yao Ko
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Patent number: 8669133Abstract: The present disclosure provides an image sensor semiconductor device. The semiconductor device includes a semiconductor substrate having a first type of dopant; a semiconductor layer having a second type of dopant different from the first type of dopant and disposed on the semiconductor substrate; and an image sensor formed in the semiconductor layer.Type: GrantFiled: May 14, 2010Date of Patent: March 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Wei Chang, Han-Chi Liu, Chun-Yao Ko, Shou-Gwo Wuu
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Publication number: 20140059278Abstract: Storage device FirmWare (FW) and manufacturing software techniques include access to FW images and communication of a manufacturing software tool. The manufacturing software tool enables download of the FW images into an I/O device and controlling a manufacturing test of the I/O device that is a storage device providing a storage capability. Execution of the downloaded FW images enables an I/O controller of the I/O device to provide the storage capability via operation with one or more selected types of flash memory devices. The selected types are selected from a plurality of flash memory types that the I/O controller is capable of operating with by executing appropriate ones of the FW images. Optionally the manufacturing test includes testing the storage capability of the I/O device. The techniques further include an SSD manufacturing self-test capability.Type: ApplicationFiled: November 12, 2012Publication date: February 27, 2014Applicant: LSI CORPORATIONInventors: Karl David Schuh, Karl Huan-Yao Ko, Aloysius C. Ashley Wijeyeratnam, Steven Gaskill, Thad Omura, Sumit Puri, Jeremy Isaac Nathaniel Werner
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Patent number: 8653623Abstract: A one-time programmable (OTP) device includes at least one transistor that is electrically coupled with a fuse. The fuse includes a silicon-containing line continuously extending between a first node and a second node of the fuse. A first silicide-containing portion is disposed over the silicon-containing line. A second silicide-containing portion is disposed over the silicon-containing line. The second silicide-containing portion is separated from the first silicide-containing portion by a predetermined distance. The predetermined distance is substantially equal to or less than a length of the silicon-containing line.Type: GrantFiled: May 13, 2011Date of Patent: February 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jyun-Ying Lin, Chun-Yao Ko, Ting-Chen Hsu
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Publication number: 20140016399Abstract: One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.Type: ApplicationFiled: July 13, 2012Publication date: January 16, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui