Abstract: A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip. The second substrate layer is substantially smaller than the first substrate layer, is formed on the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.

Abstract: A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip. The second substrate layer is substantially smaller than the first substrate layer, is formed on the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.

Abstract: A method for out-of-plane displacement detection is disclosed. The out-of-plane displacement is detected by analyzing all the fringe density indexes calculated using the frequency-domain information extracted from a series of interference images of the sample vibrating at different frequencies. The present invention further discloses a method and an apparatus for resonant frequency identification by detecting the peak value of all the fringe indexes calculated at different scanning frequencies. With the identified resonant frequency, the full-field vibratory surface profile of the sample in various resonance modes can be reconstructed.

Abstract: A leadframe of a leadless flip-chip package includes a plurality of inner leads, a nonconductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower surfaces of the redistribution lead portions, and is filled with the non-conductive ink layer. The non-conductive ink layer fixes the redistribution lead portions onto the bump-connecting terminals. The solder mask layer is easily formed on the non-conductive ink layer and covers the inner leads.

Abstract: A semiconductor package includes a semiconductor chip, a first substrate layer and a second substrate layer. The semiconductor chip has an active surface and a plurality of pads disposed on the active surface. The first substrate layer is formed on the active surface of the semiconductor chip and has a plurality of first contacts electrically connected to the pads of the semiconductor chip. The second substrate layer is substantially smaller than the first substrate layer, is formed on the first substrate layer, and has a plurality of second contacts electrically connected to the first contacts of the first substrate layer.

Abstract: A leadframe of a leadless flip-chip package includes a plurality of inner leads, a non-conductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower surfaces of the redistribution lead portions, and is filled with the non-conductive ink layer. The non-conductive ink layer fixes the redistribution lead portions onto the bump-connecting terminals. The solder mask layer is easily formed on the non-conductive ink layer and covers the inner leads.

Abstract: The present invention relates to a substrate structure having a solder mask and a process for making the same. The process comprises: (a) providing a substrate having a top surface, the top surface having a die pad and a plurality of solder pads; (b) forming a first solder mask on the top surface, the first solder mask having a plurality of openings, each opening corresponding to each solder pad so as to expose at least part of the solder pad; and (c) forming a second solder mask on the first solder mask. Whereby, the substrate structure of the invention can be used for packaging a thicker die so as to prevent the die crack and the overflow of molding compound will be avoided.

Abstract: A leadframe for multi-chip package (MCP) including a die pad and a plurality of leads. A dielectric layer is formed on the lower surface of the die pad, so that the die pad is etched to form an interconnecting conductor with a bonding region. An insulation layer is formed on the interconnecting conductor and exposes the bonding region, so that a chip or a passive component can be electrically connected to the leads via the interconnecting conductor.

Abstract: A leadframe with a chip pad for two-sided stacking including a chip pad and a plurality of leads is disclosed. A dielectric adhesive layer is formed on the lower surface of the chip pad and is adhered onto a first trace layer, which has a connecting pad. At least a through hole passes through the chip pad, the dielectric adhesive layer and the first trace layer. An electrically-conductive material is formed inside the through hole for electrically connecting the connecting pad of the first trace layer to the chip pad. When an electronic component is mounted on the lower surface of the chip pad, a plurality of bonding wires having one ends on the upper surface of the chip pads can electrically connect the electronic component to the leads for achieving two-sided stacking of the chip pad.

Abstract: A multi-row substrate strip mainly comprises a plurality of first and second substrate units in parallel, a plurality of connecting bars, a degating metal layer and at least one plating layer. The connecting bars are used to connect the first substrate units and connect the second substrate units. The degating metal layer comprises a plurality of runner portions on the connecting bars, a plurality of first gate portions and a plurality of second gate portions. The first gate portions are formed on the first substrate units, and the second gate portions are formed on the second substrate units. The plating layer is formed on the first gate portions and the second gate portions, and exposes the runner portions, so as to save the plating material.

Abstract: A circuitized substrate with trace embedded inside ground layer mainly comprises a trace layer, a first dielectric layer, a ground layer, a second dielectric layer, and at least one embedded conductive trace. The embedded conductive trace is located between the first dielectric layer and the second dielectric layer. The embedded conductive trace is hidden inside a hollow portion of the ground layer, and is electrically insulated from the ground layer. Therefore, by utilizing the embedded conductive trace, the traces of the trace layer can be decreased and the product yield can be improved.

Abstract: A semiconductor package with flip chip on leadless leadframe includes a leadless leadframe, a ring-shaped tape, a flip chip and an underfilling material. The leadframe has a plurality of inner leads. Connecting regions are defined on the upper surfaces of the inner leads. The ring-shaped tape is disposed on the upper surfaces of the inner leads and has an opening leaving the connecting regions exposed. The flip chip is bonded inside the opening of the ring-shaped tape and has a plurality of bumps connected to the connecting regions of the inner leads. The underfilling material is confined by the ring-shaped tape to be inside the opening for leaving the bumps of the flip chip exposed.

Abstract: A leadframe with a chip pad for two-sided stacking including a chip pad and a plurality of leads is disclosed. A dielectric adhesive layer is formed on the lower surface of the chip pad and is adhered onto a first trace layer, which has a connecting pad. At least a through hole passes through the chip pad, the dielectric adhesive layer and the first trace layer. An electrically-conductive material is formed inside the through hole for electrically connecting the connecting pad of the first trace layer to the chip pad. When an electronic component is mounted on the lower surface of the chip pad, a plurality of bonding wires having one ends on the upper surface of the chip pads can electrically connect the electronic component to the leads for achieving two-sided stacking of the chip pad.

Abstract: A leadframe for multi-chip package (MCP) including a die pad and a plurality of leads. A dielectric layer is formed on the lower surface of the die pad, so that the die pad is etched to form an interconnecting conductor with a bonding region. An insulation layer is formed on the interconnecting conductor and exposes the bonding region, so that a chip or a passive component can be electrically connected to the leads via the interconnecting conductor.

Abstract: A leadframe of a leadless flip-chip package includes a plurality of inner leads, a non-conductive ink layer and a solder mask layer. The inner leads have a plurality of bump-connecting terminals, a plurality of outer terminals and a plurality of redistribution lead portions. A half-etched recession is formed on lower surfaces of the redistribution lead portions, and is filled with the non-conductive ink layer. The non-conductive ink layer fixes the redistribution lead portions onto the bump-connecting terminals. The solder mask layer is easily formed on the non-conductive ink layer and covers the inner leads.

Abstract: A leadless semiconductor package mainly includes a plurality of inner leads, a chip pad, a semiconductor chip and a molding compound. A non-conductive ink is filled between every two of the inner leads, and couples the inner leads to the chip pad so as to be in replacement of the conventional tie bars. The semiconductor chip is disposed on the chip pad and electrically connected to the inner leads. Moreover, the molding compound is formed on the inner leads and the non-conductive ink for encapsulating the semiconductor chip. The non-conductive ink prevents the exposed bottom surfaces of the inner leads from contamination by the molding compound without attaching an external tape during molding. Also the inner leads can be in a multi-row arrangement and the chip pad can be disposed in an optional location.

Abstract: A method of assembling a passive component over the active surface of a die is provided. The method shortens the signal transmission path between the die and the passive component so that electrical performance of the die after packaging is improved. In addition, the transmission path and the number of contacts on the substrate for connecting the die and the passive component are reduced. With a reduction in transmission path, size of the substrate can be reduced. Furthermore, a plurality of passive components may be assembled onto the dies of a wafer in a single operation so that there is no need to assemble individual passive component over each packaging substrate.

Abstract: A die bonder includes a conveyor, a pre-heater, at least one carrier, a paste-dispensing mechanism, a die taking/placing mechanism, and a heater. The conveyor continuously operates in a ring-shaped manner. The carrier is carried on the conveyor to position the substrate. The pre-heater heats the substrate to eliminate the moisture in the substrate. The paste-dispensing mechanism dispenses an adhesive agent onto the substrate. Then, the die taking/placing mechanism places a die onto the substrate at a position where the adhesive agent is dispensed. Finally, the heater is used to cure the adhesive agent so as to bond the die to the substrate.

Abstract: A die bonder includes a conveyor, a pre-heater, at least one carrier, a paste-dispensing mechanism, a die taking/placing mechanism, and a heater. The conveyor continuously operates in a ring-shaped manner. The carrier is carried on the conveyor to position the substrate. The pre-heater heats the substrate to eliminate the moisture in the substrate. The paste-dispensing mechanism dispenses an adhesive agent onto the substrate. Then, the die taking/placing mechanism places a die onto the substrate at a position where the adhesive agent is dispensed. Finally, the heater is used to cure the adhesive agent so as to bond the die to the substrate.