Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.

Abstract: A solid-state imaging device having an analog-digital converter, and an analog-digital conversion method are described herein. An example of a solid-state imaging device includes a bit inconsistency prevention section configured to prevent bit inconsistency between output of a low-level bit latch section and a high-level bit counting section.

Abstract: There are provided an A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system. An ADC 15A is configured as an integrating-type A/D conversion circuit using a comparator 151 and a counter 152. The counter 152 has a function of switching a count mode from an up count to a down count and from a down count to an up count while a value is held, a function of performing counting at both rising and falling edges of an input clock CK at a frequency two times as high as that of the input clock, and a function of latching the input clock CK in accordance with an output signal of the comparator 151 and setting non-inverted or inverted data of the latched data to be data of an LSB.

Abstract: There is provided a solid-state imaging device, which includes: a comparator for sequentially comparing a predetermined level of an analog pixel signal obtained from a plurality of pixels with a reference signal which is gradually changed and used for converting the predetermined level into digital data; a counter for performing a count processing in parallel with a comparison processing for the predetermined level in the comparator, and holding a count value at a time of completing the comparison processing to obtain digital data indicative of a value obtained by adding the plurality of pixel signals; and an addition spatial position adjusting unit for controlling a selection operation for selecting spatial positions of the plurality of pixels to be processed in the comparator and a ratio of a weight value during the addition to adjust spatial positions of pixels after addition.

Abstract: A signal-processing method adapted to perform predetermined signal processing based on a unit signal transmitted from a semiconductor device that includes at least two unit components arranged in a predetermined order, where each of the unit components includes a detection unit configured to detect change information responsive to a change in an incident physical quantity and a unit-signal-generation unit configured to generate the unit signal based on the change information, and that detects the distribution of the physical quantity is provided. The signal-processing method includes the steps of externally transmitting operation information that can specify an operation state of the semiconductor device from the semiconductor device and performing the predetermined signal processing based on the unit signal by referring to the operation information in a signal-processing unit provided outside the semiconductor device.

Abstract: A solid-state imaging including a comparing circuit, an inverting circuit, and a masking circuit, and that performs column parallel AD conversion processing of analog pixel signals output from a plurality of pixels arranged in a two-dimensional matrix form. The comparing circuit outputs a difference signal obtained by comparing each of the pixel signals outputted from the pixels with a reference signal having a ramp waveform. The inverting circuit inverts a logic of the difference signal outputted from the comparing circuit. The masking circuit masks an output of an output signal of the inverting circuit to a circuit in a subsequent stage during an input offset canceling period in which the comparing circuit cancels an input offset between the pixel signal and the reference signal.

Abstract: A solid-state image pickup device and a camera system in which: (1) counters are organized into a counter group and a memory group on a column-by-column basis; (2) in each column, the individual counters are cascade-connected between individual bits; (3) switches are provided at bit output portions of the individual counters; (4) connecting sides of the individual switches are commonly connected to a column-signal transfer line, and output sides of the switches are shared with the other individual bits; (5) inputs of memories (latch circuits), which store digital data for horizontal transfer, share the column-signal transfer line; and (6) outputs of the memories corresponding to the individual bits are connected via switches to data transfer signal lines wired so as to be orthogonal to the column-signal transfer line.

Abstract: A solid-state imaging includes a comparing circuit, an inverting circuit, and a masking circuit, and performs column parallel AD conversion processing of analog pixel signals outputted from a plurality of pixels arranged in a two-dimensional matrix form. The comparing circuit outputs a difference signal obtained by comparing each of the pixel signals outputted from the pixels with a reference signal having a ramp waveform. The inverting circuit inverts a logic of the difference signal outputted from the comparing circuit. The masking circuit masks an output of an output signal of the inverting circuit to a circuit in a subsequent stage during an input offset canceling period in which the comparing circuit is canceling an input offset between the pixel signal and the reference signal.

Abstract: A signal processing circuit includes: a reference signal generating circuit that generates a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current; and a signal processing unit including a plurality of processing sections that process the reference signal as a ramp wave and a potential of a supplied analog signal, wherein the reference signal processing circuit has a function of adjusting an offset of the reference signal by adjusting the current from the time of starting the generation of the reference signal or adjusting the level of the reference signal at least at the time of starting the generation of the reference signal.

Abstract: A solid state image capturing apparatus is disclosed. A pixel array section has unit pixels containing photoelectric conversion elements, the unit pixels being two-dimensionally arranged in a matrix, and column signal wires correspondingly to columns of the matrix of the unit pixels. A line scanning section selectively controls lines of the matrix of the unit pixels of the pixel array section. An analog-to-digital conversion section converts an analog signal outputted from unit pixels of a line of the matrix of the unit pixels selected by the line scanning section through a corresponding column signal line to a digital signal. A conversion clock supply section selectively generates a conversion clock having a first clock period or a second clock period. An addition section adds unit pixel digital signals converted in the analog-to-digital conversion section by the conversion clocks having the first clock period and the second clock period, respectively.

Abstract: A solid-state image pickup device and a camera system in which: (1) counters are organized into a counter group and a memory group on a column-by-column basis; (2) in each column, the individual counters are cascade-connected between individual bits; (3) switches are provided at bit output portions of the individual counters; (4) connecting sides of the individual switches are commonly connected to a column-signal transfer line, and output sides of the switches are shared with the other individual bits; (5) inputs of memories (latch circuits), which store digital data for horizontal transfer, share the column-signal transfer line; and (6) outputs of the memories corresponding to the individual bits are connected via switches to data transfer signal lines wired so as to be orthogonal to the column-signal transfer line.

Abstract: A solid-state imaging device including: a pixel section formed by a matrix-like array of a plurality of pixels performing photoelectric conversion; and a pixel signal readout section reading out a pixel signal from the pixel section in units for reading each formed by a plurality of pixels, wherein the pixel signal readout section includes a column-parallel type ADC group formed by a plurality of analog-digital converters (ADCs) for performing A-D conversion of a pixel reset level, and a signal processing system, the signal processing system obtaining only an average value of results of A-D conversion of pixel reset levels for a plurality of pixels and automatically adjusting an input offset value for the conversion range of the ADCs such that the average value of pixel reset levels will be adequately positioned with respect to the A-D conversion range.

Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.

Abstract: An NchMOS transistor Q71 on the input side of a current mirror 70 is made function as a voltage operating-point setting portion so that a pixel signal line potential (voltage of a horizontal signal line 20) would be constantly stable nearly at the GND. Then, an amplification factor and linearity become good in an amplification transistor in the solid imaging device 3. A current copier 90 is made function as a current sampling portion so as to receive a signal current IIN of the solid imaging device 3 through the current mirror 70 to carry out sampling of a pixel signal in a resetting period in the shape of current component as the pixel signal is. Calculating differential between a current component in a detecting period and an offset current, which is the current component in a resetting period in sampling, allows an offset component included in the pixel signal to be removed and only pure signal Isig to be picked up at an output terminal Iout, so that the FPN restraining function can be fulfilled.

Abstract: There are provided an A/D conversion circuit in which a counter is made to be capable of performing counting at both edges of a clock, up/down count values can be switched while the up/down count values are held, and the duty of the counting operation is difficult to be distorted even with the both-edge counting, a solid-state image sensor, and a camera system. An ADC 15A is configured as an integrating-type A/D conversion circuit using a comparator 151 and a counter 152. The counter 152 has a function of switching a count mode from an up count to a down count and from a down count to an up count while a value is held, a function of performing counting at both rising and falling edges of an input clock CK at a frequency two times as high as that of the input clock, and a function of latching the input clock CK in accordance with an output signal of the comparator 151 and setting non-inverted or inverted data of the latched data to be data of an LSB.

Abstract: A dc level control method for holding a dc level of a clamp portion in an electric signal to be a prescribed value is disclosed, wherein the method comprises the steps of: comparing a dc level of a sampling interval in said electric signal with a predetermined reference value to obtain a difference between said dc level and said reference value using an A/D converting section for dc level comparison which has a lower bit resolution than an A/D converting section for digital signal processing of said electric signal; and feeding back a clamp signal to said electric signal so that said obtained difference between said dc level and said reference value substantially becomes zero. This method is suitable for applying to a signal processing system for a solid state imaging apparatus.

Abstract: A solid-state image pickup device and a camera system in which: (1) counters are organized into a counter group and a memory group on a column-by-column basis; (2) in each column, the individual counters are cascade-connected between individual bits; (3) switches are provided at bit output portions of the individual counters; (4) connecting sides of the individual switches are commonly connected to a column-signal transfer line, and output sides of the switches are shared with the other individual bits; (5) inputs of memories (latch circuits), which store digital data for horizontal transfer, share the column-signal transfer line; and (6) outputs of the memories corresponding to the individual bits are connected via switches to data transfer signal lines wired so as to be orthogonal to the column-signal transfer line.

Abstract: A solid state image capturing apparatus is disclosed. A pixel array section has unit pixels containing photoelectric conversion elements, the unit pixels being two-dimensionally arranged in a matrix, and column signal wires correspondingly to columns of the matrix of the unit pixels. A line scanning section selectively controls lines of the matrix of the unit pixels of the pixel array section. An analog-to-digital conversion section converts an analog signal outputted from unit pixels of a line of the matrix of the unit pixels selected by the line scanning section through a corresponding column signal line to a digital signal. A conversion clock supply section selectively generates a conversion clock having a first clock period or a second clock period. An addition section adds unit pixel digital signals converted in the analog-to-digital conversion section by the conversion clocks having the first clock period and the second clock period, respectively.

Abstract: A solid-state imaging includes a comparing circuit, an inverting circuit, and a masking circuit, and performs column parallel AD conversion processing of analog pixel signals outputted from a plurality of pixels arranged in a two-dimensional matrix form. The comparing circuit outputs a difference signal obtained by comparing each of the pixel signals outputted from the pixels with a reference signal having a ramp waveform. The inverting circuit inverts a logic of the difference signal outputted from the comparing circuit. The masking circuit masks an output of an output signal of the inverting circuit to a circuit in a subsequent stage during an input offset canceling period in which the comparing circuit is canceling an input offset between the pixel signal and the reference signal.

Abstract: A solid-state image pickup apparatus and an image pickup method are disclosed which can detect and correct fixed pattern noise efficiently and accurately. Pickup image signals produced by reading out signals in parallel from a pixel sensor section are subject to an analog gain process, an A/D conversion process and a digital gain process. Within a period within which the pickup image signals which are based on a fixed value are inputted within a one-frame period, a reference signal average is produced from the signals. Sum values of difference values of the signals from the reference signal average are stored. Within a period within which the pickup image signals from valid pixels are inputted within the one-frame period, fixed pattern noise is removed from the pickup image signals using division averages obtained by dividing the stored sum values.