Abstract: A second DC power-supply voltage that is obtained by outputting a first DC power-supply voltage obtained by converting an AC power supply into a direct current in an AC-DC converter circuit, through a first switch for PWM switching is smoothed and fed to a load as an output DC power-supply voltage. The first DC power-supply voltage is also supplied to a battery through a third switch for PWM switching and the battery is thereby charged. Further, a third power-supply voltage output from the battery is output to the output side of the first switch through a fourth switch for PWM switching.

Abstract: A second DC power-supply voltage that is obtained by outputting a first DC power-supply voltage obtained by converting an AC power supply into a direct current in an AC-DC converter circuit, through a first switch for PWM switching is smoothed and fed to a load as an output DC power-supply voltage. The first DC power-supply voltage is also supplied to a battery through a third switch for PWM switching and the battery is thereby charged. Further, a third power-supply voltage output from the battery is output to the output side of the first switch through a fourth switch for PWM switching.

Abstract: A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.

Abstract: A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film.

Abstract: A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.

Abstract: In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.

Abstract: A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.

Abstract: A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.

Abstract: The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.

Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

Abstract: A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film.

Abstract: A stacked semiconductor device includes a plurality of semiconductor chips and a conductive path extending through at least one of the semiconductor chips. The semiconductor chips are stacked together. The semiconductor chips are electrically connected by the conductive path, and the conductive path has a plurality of through-connections extending through the corresponding semiconductor chip.

Abstract: A three-dimensional semiconductor memory device having the object of decreasing the interconnection capacitance that necessitates electrical charge and discharge during data transfer and thus decreasing power consumption is provided with: a plurality of memory cell array chips, in which sub-banks that are the divisions of bank memory are organized and arranged to correspond to input/output bits, are stacked on a first semiconductor chip; and interchip interconnections for connecting the memory cell arrays such that corresponding input/output bits of the sub-banks are the same, these interchip interconnections being provided in a number corresponding to the number of input/output bits and passing through the memory cell array chips in the direction of stacking.

Abstract: In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signals, only one interchip interconnection that serves for signal transmission is selected and other interchip interconnections are electrically isolated by means of switches that are provided between the interchip interconnections and signal lines. Interchip interconnection capacitance relating to the charge and discharge of interconnections is thus minimized.

Abstract: The stacked semiconductor memory device of the present invention has the object of reducing the cost of developing a wide variety of memory devices and includes: a memory cell array chip that is equipped with memory cell arrays, an interface chip that is stacked with the memory cell array chip and that is provided with a memory configuration switching circuit for changing the input/output bit configuration of the memory cell arrays, and a plurality of interchip wires for connecting the memory cell array chip and the interface chip.

Abstract: A latch conversion circuit which is to be added to a basic logic circuit to obtain a latch circuit having an extremely small through delay amount is prepared in advance. Moreover, provided is means for obtaining a latch circuit position whereat the shifting of the clock edge, such as skew or jitter, can be absorbed to the maximum extent possible, and for forming a latch circuit by adding the latch conversion circuit to the basic logic circuit located at the obtained point. Accordingly, a latch circuit which is not, to the extent possible, affected by skew or jitter can be designed.

Abstract: The present invention provides for adjusting the delay time interval of an input signal by controlling the internal register value and internal signal in a semiconductor integrated circuit device, or an external signal. The invention comprises a first gate array 10 for carrying out fine adjustment of the delay time interval of the input signal, capacitances 60 to 63 and 70 to 73 connected to the output side of a specified gate in the first gate array via first switching device 40 to 43, a second gate array 20 for carrying out rough adjustment of the delay time interval of the input signal; and a control device 30 that adjusts the delay time interval of the input signal by adjusting the capacitances connected to the output side of a specified gate in the first gate array and the number of gate stages in the second gate array 20.

Abstract: A semiconductor integrated circuit includes a first transistor of a first conductivity-type having a source connected to a first source line and a drain; a second transistor of a second conductivity-type having a source connected to a second source line and a drain; and a plurality of third transistors of the second conductivity-type connected in series between the drain of the first transistor and the drain of said second transistor, each of said third transistors having a gate for receiving an input signal. The second transistor and at least one and not all of the third transistors have a threshold voltage lower than a threshold voltage of the others of the third transistors.

Abstract: A semiconductor integrated circuit enables a drive circuit and a reception circuit to be constituted. The drive circuit drives long wiring in high speed while achieving realization of reduced area when large capacity of load is driven. The reception circuit receives this signal in high speed. There is provided an inverter within the drive circuit. An n-type MOS transistor is adopted as drive transistor. Drive power of the n-type MOS transistor is larger than that of a p-type MOS transistor. It is capable of driving signal with large load in long wiring such as bus line. Thus the drive circuit is realized in that the drive circuit drives the long wiring in high speed while achieving realization of reduced area. Further, it is capable of realizing a reception circuit suppressing through-current during the time period when the signal is changed.

Abstract: A semiconductor integrated circuit enables a drive circuit and a reception circuit to be constituted. The drive circuit drives long wiring in high speed while achieving realization of reduced area when large capacity of load is driven. The reception circuit receives this signal in high speed. There is provided an inverter within the drive circuit. An n-type MOS transistor is adopted as drive transistor. Drive power of the n-type MOS transistor is larger than that of a p-type MOS transistor. It is capable of driving signal with large load in long wiring such as bus line. Thus the drive circuit is realized in that the drive circuit drives the long wiring in high speed while achieving realization of reduced area. Further, it is capable of realizing a reception circuit suppressing through-current during the time period when the signal is changed.