Abstract: Disclosed herein is a semiconductor integrated circuit comprising: a first transistor of a first conductivity-type having a source connected to a first source line and a drain; a second transistor of a second conductivity-type having a source connected to a second source line and a drain; and a plurality of third transistors of said second conductivity-type connected in series between the drain of said first transistor and the drain of said second transistor, each of said third transistors having a gate for receiving an input signal, said second transistor and at least one and not all of said third transistors having a threshold voltage lower than a threshold voltage of the others of said third transistors. The circuit of the present invention including the transistors having the different threshold values can achieve the high speed operation of the circuit, the extension of the signal retention time secured by the reduction of a leakage current and the decrease of the power consumption.

Abstract: The present invention provides for adjusting the delay time interval of an input signal by controlling the internal register value and internal signal in a semiconductor integrated circuit device, or an external signal. The invention comprises a first gate array 10 for carrying out fine adjustment of the delay time interval of the input signal, capacitances 60 to 63 and 70 to 73 connected to the output side of a specified gate in the first gate array via first switching device 40 to 43, a second gate array 20 for carrying out rough adjustment of the delay time interval of the input signal; and a control device 30 that adjusts the delay time interval of the input signal by adjusting the capacitances connected to the output side of a specified gate in the first gate array and the number of gate stages in the second gate array 20.

Abstract: A semiconductor integrated circuit enables a drive circuit and a reception circuit to be constituted. The drive circuit drives long wiring in high speed while achieving realization of reduced area when large capacity of load is driven. The reception circuit receives this signal in high speed. There is provided an inverter within the drive circuit. An n-type MOS transistor is adopted as drive transistor. Drive power of the n-type MOS transistor is larger than that of a p-type MOS transistor. It is capable of driving signal with large load in long wiring such as bus line. Thus the drive circuit is realized in that the drive circuit drives the long wiring in high speed while achieving realization of reduced area. Further, it is capable of realizing a reception circuit suppressing through-current during the time period when the signal is changed.

Abstract: Disclosed herein is a semiconductor integrated circuit comprising: a first transistor of a first conductivity-type having a source connected to a first source line and a drain; a second transistor of a second conductivity-type having a source connected to a second source line and a drain; and a plurality of third transistors of said second conductivity-type connected in series between the drain of said first transistor and the drain of said second transistor, each of said third transistors having a gate for receiving an input signal, said second transistor and at least one and not all of said third transistors having a threshold voltage lower than a threshold voltage of the others of said third transistors. The circuit of the present invention including the transistors having the different threshold values can achieve the high speed operation of the circuit, the extension of the signal retention time secured by the reduction of a leakage current and the decrease of the power consumption.

Abstract: A floating point multiplier includes an exponential part adder for receiving and adding exponential parts of a multiplied value and a multiplying value and outputting an exponential addition result, a binary multiplier for receiving and multiplying mantissa of the multiplied value and the multiplying value and for outputting the multiplication result, an OR gate inputting for receiving a predetermined number of lower order bits of the multiplication result and outputting a logical sum of the lower order bits as a sticky bit, rounding process and normalization process circuit for receiving a predetermined number of higher order bits of the multiplication result and the sticky signal, performing a rounding process and a normalizing process for the higher order bits of the multiplication result on the basis of the sticky bit, coupling a result of normalization with the addition result of the exponential parts and outputting a final multiplication result, and a selection circuit for receiving the final multiplica

Abstract: A multiplier circuit has a partial AND generating portion generating n in number of partial AND's as products of a multiplied value and respective bits of n-bit multiplying value, an intermediate sum generating portion inputting n in number of partial AND's, generating intermediate sums and reducing number of the intermediate sums progressively for finally outputting two intermediate sums, and an adder adding two intermediate sums output from the intermediate sum generating portions for outputting a product of multiplication of the multiplied value and the multiplying value. The intermediate sum generating portion has a plurality of intermediate sum calculating circuits, each of which has a plurality of adders of the type of four inputs and two outputs, connected in parallel, the intermediate sum calculating circuits are connected in a plurality of stages in a tree-like configuration.

Abstract: An artificial random-number pattern generating circuit has a plurality of flip-flops each having a set signal input terminal and a clock signal input terminal; a plurality of selectors each of which forwards its output to the corresponding flip-flop and receives a first operation mode signal and/or a second operation mode signal; and an exclusive logical OR gate. The artificial random-number pattern generating circuit functions in three different ways, that is, as an artificial random-number pattern generator, a boundary scanning buffer or an input buffer, in accordance with the combinations of the first and second operation mode signals. The circuit can make not only a diagnosis of failure in the internal circuit of the large-scale integration (LSI) but also overall tests including those for input and output buffer circuits of the mounted LSI chip on a board or those for external wirings for the LSI.

Abstract: A multiplying circuit is able to perform a multiplication of n bits.times.n bits at a high speed by increasing the speed of the forming process of the partial products so that the delay time may be inhibited from increasing for a large n, and which can inhibit the chip size from becoming large. A 6-bit multiplier (Y1 to Y6) is divided into bit sets each having plural bits. The thus divided sets are inputted respectively into booth decoders 1A to 1C to generate three-bit interim outputs m1 to m3. On the other hand, partial product generating circuits 2A, 2B and 2C receive a multiplicand X of plural bits to form partial products p1, p2 and p3 respectively by multiplying the multiplicand X with the interim outputs m1, m2 and m3. These partial products p1 to p3 are transformed in a first full adder allay 3 into interim sums r1 and r2. The thus formed interim sums r1 and r2 are added in a second full adder allay 4 with a value.