Patents by Inventor Yasuhiko Ueda

Yasuhiko Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8877079
    Abstract: The present invention relates to a method of manufacturing a semiconductor device wherein etching is performed on films on a wafer using a plasma treatment apparatus. In the manufacturing method according to the present invention, a change in the difference between the emission intensities of a first wavelength component and a second wavelength component in plasma is monitored during etching. If the amount of change in the difference per unit time exceeds a predetermined threshold a given number of times in a row, then the flow rate of oxygen introduced to the plasma treatment apparatus is increased or, if the amount of change exceeding the predetermined threshold has not been seen, then the oxygen flow rate is set back to the original value thereof. This series of actions is repeated all the time during a set period of time.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: November 4, 2014
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Yasuhiko Ueda
  • Patent number: 8729626
    Abstract: A semiconductor device may include, but is not limited to: a semiconductor structure extending upwardly; a first insulating film covering at least a side surface of the semiconductor structure; a gate electrode extending upwardly, the gate electrode being adjacent to the first insulating film; and an insulating structure extending upwardly, the insulating structure being adjacent to the gate electrode.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: May 20, 2014
    Inventors: Yu Kosuge, Yasuhiko Ueda
  • Publication number: 20140134487
    Abstract: An electric storage device includes an electrolyte and an electric storage unit including a positive electrode including a positive-electrode collector electrode and a positive-electrode active-material layer disposed on the positive-electrode collector electrode; a negative electrode including a negative-electrode collector electrode and a negative-electrode active-material layer disposed on the negative-electrode collector electrode and facing the positive-electrode active-material layer; a first insulating layer bonded to the positive electrode and the negative electrode to isolate the positive electrode and the negative electrode from each other; and a region that is sealed with the first insulating layer in plan view and that holds the electrolyte between the positive electrode and the negative electrode, wherein an air permeability P of the first insulating layer satisfies the formula 1250 s/100 cc<P<95000 s/100 cc.
    Type: Application
    Filed: December 19, 2013
    Publication date: May 15, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Masaharu Itaya, Keiji Horikawa, Manabu Sawada, Hiroyuki Harada, Yuusuke Ueba, Yukio Ehara, Yasuhiko Ueda, Yasutake Fukuda
  • Publication number: 20140106191
    Abstract: An electrical storage unit that includes a positive electrode, which includes a positive-electrode collector electrode and a positive-electrode active material layer on the positive-electrode collector electrode, a negative electrode, which includes a negative-electrode collector electrode and a negative-electrode active material layer on the negative-electrode collector electrode, the negative-electrode active material layer facing the positive-electrode active material layer, and a first insulating layer bonded to the positive electrode and the negative electrode and separating the positive electrode from the negative electrode. The first insulating layer is bonded to part of a surface of the positive electrode and part of a surface of the negative electrode and includes a communication path for connecting the outside of the electrical storage unit to the inside of the electrical storage unit.
    Type: Application
    Filed: December 17, 2013
    Publication date: April 17, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Masaharu Itaya, Keiji Horikawa, Manabu Sawada, Hiroyuki Harada, Yuusuke Ueba, Yukio Ehara, Yasuhiko Ueda, Yasutake Fukuda
  • Publication number: 20140106213
    Abstract: A highly-reliable electrical storage device element and electrical storage device, in each of which on predetermined regions of predetermined end surfaces of a laminate forming an electrical storage component, sprayed end surface electrodes each having a high bond strength to the laminate are provided.
    Type: Application
    Filed: December 27, 2013
    Publication date: April 17, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Keiji Horikawa, Hiroki Horiguchi, Yukio Ehara, Yasuhiko Ueda, Hiroyuki Harada, Masaharu Itaya, Yasutake Fukuda, Shigeo Hayashi
  • Patent number: 8637364
    Abstract: An amorphous carbon film and an interlayer insulation film are formed in a memory cell region and a peripheral circuit region, respectively. An insulating film is formed on the amorphous carbon film and the interlayer insulation film. A portion of the insulating film that corresponds to capacitors on the amorphous carbon film is removed so that lower electrodes of the capacitors are supported from opposite sides of the lower electrodes. An insulating film pattern continuously extends from the memory cell region to the peripheral circuit region wholly covered with the insulating film pattern. Subsequently, the amorphous carbon film is removed to leave the capacitors supported by the insulating film pattern on both sides of the lower electrodes.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: January 28, 2014
    Inventor: Yasuhiko Ueda
  • Publication number: 20140017587
    Abstract: A solid oxide fuel cell bonding material contains a glass ceramic layer containing glass ceramic, and a constrained layer laminated on the glass ceramic layer. A solid oxide fuel cell employing the solid oxide fuel cell bonding material is also described.
    Type: Application
    Filed: September 18, 2013
    Publication date: January 16, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Yasuhiko Ueda
  • Publication number: 20130280569
    Abstract: An element body having a plurality of positive electrode layers, a plurality of negative electrode layers, and separator layers each interposed between adjacent positive and negative electrode layers. A package includes a box-like package body portion containing the element body, and a flat package edge portion connected to the package body portion. A positive electrode terminal and a negative electrode terminal are bent at terminal body portions extending outward from the package edge portion to form a positive-electrode bent portion and a negative-electrode bent portion, respectively. The bent portions are joined to the package edge portion, with joining members.
    Type: Application
    Filed: June 20, 2013
    Publication date: October 24, 2013
    Inventors: Atsutaka Mori, Yasuhiko Ueda, Takayuki Hata, Masaki Takauchi
  • Patent number: 8513809
    Abstract: A semiconductor device includes an interlayer insulation film, a wiring embedded in the interlayer insulation film and an air gap part formed between a side surface of the wiring and the interlayer insulation film. A first sidewall film is formed in the air gap part so that the first sidewall film contacts with the side surface of the wiring.
    Type: Grant
    Filed: May 6, 2011
    Date of Patent: August 20, 2013
    Assignee: Elpida Memory, Inc.
    Inventor: Yasuhiko Ueda
  • Publication number: 20120329236
    Abstract: A method of manufacturing a device includes: forming a fifth insulating film on a semiconductor substrate having a peripheral circuit region and a memory cell region in which a contact pad is formed; forming a second sacrifice film in the memory cell region in which the fifth insulating film is formed; forming, after the forming of the second sacrifice, a second insulating film in the peripheral circuit region on the semiconductor substrate to have a sidewall coming into contact with the second sacrifice film; forming a third insulating film to cover an upper surface of the second sacrifice film and an upper surface of the second insulating film; forming a hole penetrating through the third insulating film, the second sacrifice film and the fifth insulating film in the memory cell region; forming a lower electrode in the hole; and removing all of the second sacrifice film.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 27, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Yasuhiko UEDA
  • Publication number: 20120273922
    Abstract: An amorphous carbon film and an interlayer insulation film are formed in a memory cell region and a peripheral circuit region, respectively. An insulating film is formed on the amorphous carbon film and the interlayer insulation film. A portion of the insulating film that corresponds to capacitors on the amorphous carbon film is removed so that lower electrodes of the capacitors are supported from opposite sides of the lower electrodes. An insulating film pattern continuously extends from the memory cell region to the peripheral circuit region wholly covered with the insulating film pattern. Subsequently, the amorphous carbon film is removed to leave the capacitors supported by the insulating film pattern on both sides of the lower electrodes.
    Type: Application
    Filed: April 25, 2012
    Publication date: November 1, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: YASUHIKO UEDA
  • Publication number: 20110278654
    Abstract: A semiconductor device comprises an interlayer insulation film, a wiring embedded in the interlayer insulation film and an air gap part formed between a side surface of the wiring and the interlayer insulation film.
    Type: Application
    Filed: May 6, 2011
    Publication date: November 17, 2011
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Yasuhiko UEDA
  • Publication number: 20110108910
    Abstract: A semiconductor device may include, but is not limited to: a semiconductor structure extending upwardly; a first insulating film covering at least a side surface of the semiconductor structure; a gate electrode extending upwardly, the gate electrode being adjacent to the first insulating film; and an insulating structure extending upwardly, the insulating structure being adjacent to the gate electrode.
    Type: Application
    Filed: November 8, 2010
    Publication date: May 12, 2011
    Applicant: ELPIDA MEMORY, INC
    Inventors: Yu KOSUGE, Yasuhiko UEDA
  • Patent number: 7858508
    Abstract: In a method of manufacturing a semiconductor device, a trench is formed to have an upper quadrangular section and a lower circular section which is formed through a hydrogen annealing process, to extend in a depth direction of a semiconductor substrate. An insulating film is formed on a surface of the trench and a surface of the semiconductor substrate. A conductive film is formed to fill the trench whose surface is covered with the an insulating film. Source/drain regions are formed on both sides of the trench.
    Type: Grant
    Filed: March 14, 2007
    Date of Patent: December 28, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroyuki Fujimoto, Yasuhiko Ueda, Fumiki Aiso, Yuki Koga
  • Patent number: 7829418
    Abstract: A semiconductor apparatus including a trench gate transistor having at least an active region surrounded by a device isolation insulating film; a trench provided by bringing both ends thereof into contact with the device isolation insulating film in the active region; a gate electrode formed in the trench via a gate insulating film; and a diffusion layer formed close to the trench; on a semiconductor substrate, and also includes an opening portion positioned on one surface of the semiconductor substrate; a pair of first inner walls positioned in a side of the device isolation insulating film and connected with the opening portion; a pair of second inner walls positioned in a side of the active region and connected with the opening portion; and a bottom portion positioned opposite to the opening portion and connected with the first inner walls and the second inner walls, wherein a cross sectional outline of the second inner wall is substantially linear, and a burr generated inside the trench is removed or redu
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: November 9, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Yasuhiko Ueda, Hiroyuki Fujimoto
  • Publication number: 20100207202
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film, a second insulating film, and a conductive layer. The semiconductor substrate includes a pillar portion extending from a main surface of the semiconductor substrate. The first insulating film covers a side surface of the pillar portion. The second insulating film covers the main surface of the semiconductor substrate. The second insulating film is thicker than the first insulating film. The conductive layer extends along the first insulating film.
    Type: Application
    Filed: February 16, 2010
    Publication date: August 19, 2010
    Applicant: ELPIDA MEMORY, INC
    Inventor: Yasuhiko UEDA
  • Patent number: 7696569
    Abstract: A semiconductor device includes a trench provided in a semiconductor substrate, a gate electrode formed in the trench through a gate dielectric film, and a diffusion layer formed in the vicinity of the trench. The trench includes an opening portion provided in a surface of the semiconductor substrate, a recess curved surface portion including a cross-sectional contour having a substantially circular arc shape, and a connection curved surface portion connecting the recess curved surface portion and the opening portion. The connection curved surface portion includes a continuous curved surface between the opening portion and the recess curved surface portion.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: April 13, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroyuki Fujimoto, Yasuhiko Ueda
  • Patent number: 7615460
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming a conductive hard mask coupled to the semiconductor substrate via discharge plugs on a thick insulating film, selectively etching the thick insulating film by using the conductive hard mask to form cylindrical holes in the thick insulating film. The resultant cylindrical holes are free form bowing structure.
    Type: Grant
    Filed: May 5, 2006
    Date of Patent: November 10, 2009
    Assignee: Elpida Memory, Inc.
    Inventor: Yasuhiko Ueda
  • Publication number: 20090258469
    Abstract: In a method of manufacturing a semiconductor device, a carbon-containing film having electrical conductivity is formed so as to cover a first insulating film, a discharge plug and a conductor plug. A first conductive film is formed so as to pass through the carbon-containing film and to be in contact with the conductor plug. The first conductive film is exposed by removing the carbon-containing film.
    Type: Application
    Filed: April 14, 2009
    Publication date: October 15, 2009
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Yasuhiko UEDA
  • Patent number: 7589024
    Abstract: Recently, with shortened wavelengths employed in aligners, it is now difficult to use a material containing a benzene ring as a photoresist material. Since resist has extremely low plasma resistance, formation of deep holes using a photoresist as a dry etching mask is difficult. Under such circumstances, in the present invention, amorphous carbon film 6 is formed on photoresist 4 in which first hole 5 is formed, and using amorphous carbon film 6 as a mask, deep second hole 7 is formed in a etch target material such as underlying SiO2 film 2.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: September 15, 2009
    Assignee: Elpida Memory, Inc.
    Inventor: Yasuhiko Ueda