Patents by Inventor Yasuhiko Ueda
Yasuhiko Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090163007Abstract: A semiconductor device is manufactured suppressing generation of “vacancy-oxygen complex defects”. A general etching treatment is done using a general plasma gas including HBr, Cl2 and O2 till a time point when at least a part of a gate oxide film is exposed during a dry-etching step. After this time point a surface treatment is done using a plasma gas including a halogen atom having an atomic weight not less than Cl and a rare gas atom having an atomic weight not less than Ar in the same chamber. The generation of the defects which cannot be restored by heat treatment can be suppressed.Type: ApplicationFiled: December 18, 2008Publication date: June 25, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Yasuhiko UEDA
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Publication number: 20080303086Abstract: A semiconductor apparatus including a trench gate transistor having at least an active region surrounded by a device isolation insulating film; a trench provided by bringing both ends thereof into contact with the device isolation insulating film in the active region; a gate electrode formed in the trench via a gate insulating film; and a diffusion layer formed close to the trench; on a semiconductor substrate, and also includes an opening portion positioned on one surface of the semiconductor substrate; a pair of first inner walls positioned in a side of the device isolation insulating film and connected with the opening portion; a pair of second inner walls positioned in a side of the active region and connected with the opening portion; and a bottom portion positioned opposite to the opening portion and connected with the first inner walls and the second inner walls, wherein a cross sectional outline of the second inner wall is substantially linear, and a burr generated inside the trench is removed or reduType: ApplicationFiled: June 5, 2008Publication date: December 11, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Yasuhiko Ueda, Hiroyuki Fujimoto
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Publication number: 20080227225Abstract: The present invention relates to a method of manufacturing a semiconductor device wherein etching is performed on films on a wafer using a plasma treatment apparatus. In the manufacturing method according to the present invention, a change in the difference between the emission intensities of a first wavelength component and a second wavelength component in plasma is monitored during etching. If the amount of change in the difference per unit time exceeds a predetermined threshold a given number of times in a row, then the flow rate of oxygen introduced to the plasma treatment apparatus is increased or, if the amount of change exceeding the predetermined threshold has not been seen, then the oxygen flow rate is set back to the original value thereof. This series of actions is repeated all the time during a set period of time.Type: ApplicationFiled: February 29, 2008Publication date: September 18, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Yasuhiko Ueda
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Publication number: 20080153304Abstract: In a method of producing a semiconductor device, semiconductor burrs (74) are removed by dry etching using an etching gas in which a lateral-direction etch rate (R2) is greater than a depth-direction etch rate (R1) (that is, R1/R2 is smaller than 1) in a section of a groove (72) in a direction parallel to word lines.Type: ApplicationFiled: December 13, 2007Publication date: June 26, 2008Applicant: ELPIDA MEMORY, INC.Inventor: Yasuhiko Ueda
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Publication number: 20080087950Abstract: Before forming a gate trench, a buried oxide film forming an element isolation region is selectively etched, thereby exposing a side-wall shoulder portion, having a rounded shape, of an active region. This reduces a range in which an end portion of the buried oxide film serves as a mask when forming the gate trench. After this, the gate trench is formed. This makes it possible to reduce silicon that remains on a side wall of the element isolation region adjacent to the gate trench.Type: ApplicationFiled: October 16, 2007Publication date: April 17, 2008Applicant: Elpida Memory Inc.Inventor: Yasuhiko Ueda
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Publication number: 20080073709Abstract: A semiconductor device in which the reliability of a gate dielectric film is high and a channel length is sufficiently secured and a method of manufacturing the same are provided. The semiconductor device comprises a trench gate transistor. The trench gate transistor comprises: a trench provided in a semiconductor substrate; a gate electrode formed in the trench through a gate dielectric film; and a diffusion layer formed in the vicinity of the trench. The trench comprises: an opening portion provided in a surface of the semiconductor substrate; a recess curved surface portion whose cross-sectional contour is a substantially circular arc shape; and a connection curved surface portion connecting the recess curved surface portion and the opening portion. The connection curved surface portion and the recess curved surface portion are integrated in a continuous curved surface without interposing a ridge line portion therebetween.Type: ApplicationFiled: September 19, 2007Publication date: March 27, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Hiroyuki Fujimoto, Yasuhiko Ueda
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Publication number: 20070224763Abstract: In a method of manufacturing a semiconductor device, a trench is formed to have an upper quadrangular section and a lower circular section which is formed through a hydrogen annealing process, to extend in a depth direction of a semiconductor substrate. An insulating film is formed on a surface of the trench and a surface of the semiconductor substrate. A conductive film is formed to fill the trench whose surface is covered with the an insulating film. Source/drain regions are formed on both sides of the trench.Type: ApplicationFiled: March 14, 2007Publication date: September 27, 2007Applicant: ELPIDA MEMORY, INC.Inventors: Hiroyuki Fujimoto, Yasuhiko Ueda, Fumiki Aiso, Yuki Koga
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Publication number: 20070111373Abstract: Recently, with shortened wavelengths employed in aligners, it is now difficult to use a material containing a benzene ring as a photoresist material. Since resist has extremely low plasma resistance, formation of deep holes using a photoresist as a dry etching mask is difficult. Under such circumstances, in the present invention, amorphous carbon film 6 is formed on photoresist 4 in which first hole 5 is formed, and using amorphous carbon film 6 as a mask, deep second hole 7 is formed in a etch target material such as underlying SiO2 film 2.Type: ApplicationFiled: November 9, 2006Publication date: May 17, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Yasuhiko Ueda
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Publication number: 20070075433Abstract: A semiconductor device includes a substrate on which a plurality of contact holes, a plane shape of each of which is a oval, are formed and contacts formed in each of the contact holes and having oval-shaped profiles that correspond to each of the holes. The position on the perimeter of each oval at which the separation width with an oval that is adjacent to that oval is a minimum is separated by a prescribed spacing from the intersection of the perimeter of that oval and the minor axis of that oval.Type: ApplicationFiled: September 11, 2006Publication date: April 5, 2007Applicant: ELPIDA MEMORY, INC.Inventor: Yasuhiko Ueda
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Publication number: 20060255386Abstract: A method for manufacturing a semiconductor device includes the steps of forming a conductive hard mask coupled to the semiconductor substrate via discharge plugs on a thick insulating film, selectively etching the thick insulating film by using the conductive hard mask to form cylindrical holes in the thick insulating film. The resultant cylindrical holes are free form bowing structure.Type: ApplicationFiled: May 5, 2006Publication date: November 16, 2006Applicant: ELPIDA MEMORY, INC.Inventor: Yasuhiko Ueda
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Patent number: 6849539Abstract: A method for simply forming a miniature contact hole in a self-aligned manner with a wiring layer. A gate insulating film, a gate electrode, and a protective insulating layer are formed on the surface of a silicon substrate, and a blanket insulating film is deposited over the entire surface to cover a source/drain diffusion layer. Subsequently, an interlayer insulating film is laminated on the blanket insulating film. Nitrogen is added to a mixture gas of C5F8 and O2, and the resulting mixture gas is excited by a plasma for use as an etching gas. The interlayer insulating film is etched by reactive ion etching (RIE) using the blanket insulating film as an etching stopper to form a contact hole. A silicon nitride film is preferably used for the protective insulating layer. A silicon nitride film or a silicon carbide film is preferably used for the blanket insulating film.Type: GrantFiled: April 18, 2002Date of Patent: February 1, 2005Assignees: NEC Corporation, Hitachi, Ltd., NEC Electronics CorporationInventor: Yasuhiko Ueda
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Patent number: 6617245Abstract: An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.Type: GrantFiled: March 25, 2002Date of Patent: September 9, 2003Assignee: NEC Electronics CorporationInventor: Yasuhiko Ueda
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Patent number: 6569776Abstract: For selectively removing a silicon nitride film formed on a bottom of a contact hole or the like in a semiconductor device, plasma etching is performed using a process gas supplied therefor which is comprised of a first fluorine compound including a carbon atom-carbon atom bond [for example, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), octafluorocyclopentene (C5F8)], and a second fluorine compound including at least one hydrogen atom and a single carbon atom in one molecule (for example, fluoromethane (CH3F), difluoromethane (CH2F2), trifluoromethane (CHF3)]. According to this method, the silicon nitride film on the bottom can be selectively removed without removing a silicon nitride film formed on a side wall of the contact hole and the like.Type: GrantFiled: April 18, 2002Date of Patent: May 27, 2003Assignees: NEC Electronics Corporation, Hitachi, Ltd., NEC CorporationInventor: Yasuhiko Ueda
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Patent number: 6562721Abstract: There is provided a dry etching method for forming an insulating layer of SiO2 or the like in a desired shape with a substantially infinite selection property with respect to Si3N4 used as an etching stopper. As an etching gas a gas (HI, or a gas having a constitution of CxHyIz) containing iodine in a molecule is added. Here, a mixing ratio (I/C) of iodine to carbon in the etching gas is 0.3≦(I/C)≦1.5. Alternatively, instead of the iodine-containing gas the gas containing chlorine or bromine as the same halogen element is used. Since iodine, chlorine, or bromine contained in the etching gas generates a low vapor pressure material on Si3N4, Si3N4 etching is completely prohibited. Since no low vapor pressure material is generated on SiO2 or SiOF as a material to be etched, a high etching rate can be obtained.Type: GrantFiled: January 4, 2001Date of Patent: May 13, 2003Assignee: NEC Electronics CorporationInventor: Yasuhiko Ueda
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Patent number: 6559486Abstract: An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.Type: GrantFiled: November 30, 2000Date of Patent: May 6, 2003Assignee: NEC Electronics CorporationInventor: Yasuhiko Ueda
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Publication number: 20020155726Abstract: For selectively removing a silicon nitride film formed on a bottom of a contact hole or the like in a semiconductor device, plasma etching is performed using a process gas supplied therefor which is comprised of a first fluorine compound including a carbon atom-carbon atom bond [for example, octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), octafluorocyclopentene (C5F8)], and a second fluorine compound including at least one hydrogen atom and a single carbon atom in one molecule (for example, fluoromethane (CH3F) , difluoromethane (CH2F2), trifluoromethane (CHF3)]. According to this method, the silicon nitride film on the bottom can be selectively removed without removing a silicon nitride film formed on a side wall of the contact hole and the like.Type: ApplicationFiled: April 18, 2002Publication date: October 24, 2002Applicant: NEC CORPORATION, HITACHI LTD.Inventor: Yasuhiko Ueda
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Publication number: 20020155699Abstract: A method for simply forming a miniature contact hole in a self-aligned manner with a wiring layer. A gate insulating film, a gate electrode, and a protective insulating layer are formed on the surface of a silicon substrate, and a blanket insulating film is deposited over the entire surface to cover a source/drain diffusion layer. Subsequently, an interlayer insulating film is laminated on the blanket insulating film. Nitrogen is added to a mixture gas of C5F8 and O2, and the resulting mixture gas is excited by a plasma for use as an etching gas. The interlayer insulating film is etched by reactive ion etching (RIE) using the blanket insulating film as an etching stopper to form a contact hole. A silicon nitride film is preferably used for the protective insulating layer. A silicon nitride film or a silicon carbide film is preferably used for the blanket insulating film.Type: ApplicationFiled: April 18, 2002Publication date: October 24, 2002Applicant: NEC CORPORATION, HITACHI, LTD.Inventor: Yasuhiko Ueda
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Publication number: 20020115310Abstract: An etching mask having high etching selectivity for an inorganic interlayer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.Type: ApplicationFiled: March 25, 2002Publication date: August 22, 2002Inventor: Yasuhiko Ueda
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Publication number: 20010016422Abstract: There is provided a dry etching method for forming an insulating layer of SiO2 or the like in a desired shape with a substantially infinite selection property with respect to Si3N4 used as an etching stopper. As an etching gas a gas (HI, or a gas having a constitution of CxHyIz) containing iodine in a molecule is added. Here, a mixing ratio (I/C) of iodine to carbon in the etching gas is 0.3≦(I/C)≦1.5. Alternatively, instead of the iodine-containing gas the gas containing chlorine or bromine as the same halogen element is used. Since iodine, chlorine, or bromine contained in the etching gas generates a low vapor pressure material on Si3N4, Si3N4 etching is completely prohibited. Since no low vapor pressure material is generated on SiO2 or SiOF as a material to be etched, a high etching rate can be obtained.Type: ApplicationFiled: January 4, 2001Publication date: August 23, 2001Applicant: NEC CORPORATIONInventor: Yasuhiko Ueda
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Publication number: 20010002731Abstract: An etching mask having high etching selectivity for an inorganic inter layer film of SiO2 or Si3N4, an organic interlayer film such as ARC and an electrically conductive film and a contact hole using such an etching mask, a process for forming same and a resultant semiconductor device. On formation of contact holes for connecting wirings disposed through interlayer films of inorganic or organic material (20, 23 in FIG. 2), a thin film of silicon carbide (21 in FIG. 2) having high etching selectivity for any of the inorganic and organic materials is deposited on an interlayer film, and a mask pattern of silicon carbide is formed using a resist pattern (22 in FIG. 2). Thereafter, high aspect ratio contact holes having a size which is exactly same as that of the mask is formed by etching the interlayer film using the silicon carbide mask.Type: ApplicationFiled: November 30, 2000Publication date: June 7, 2001Inventor: Yasuhiko Ueda