Abstract: Disclosed is a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor. The circuit has: a first PLL circuit that is phase-locked with input horizontal synchronous signal; a second PLL circuit that is phase-locked with output of the first PLL circuit; and a circuit for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal.

Abstract: The present invention offers a tracheal smooth muscle relaxant containing the compound represented by the following formula (1) or pharmacologically acceptable salt thereof as an effective ingredient.

Abstract: The present invention offers a tracheal smooth muscle relaxant containing the compound represented by the following formula (1) or pharmacologically acceptable salt thereof as an effective ingredient.

Abstract: There is disclosed a phase-locked loop (PLL) circuit for use in an improved deflection correction circuit for a larger and flat display device. The PLL circuit has a phase comparator circuit, a filter, and a voltage-controlled oscillator (VCO) connected in series in this order. The output signal from the VCO is fed back to the phase comparator circuit. The PLL circuit further includes a period-detecting circuit for detecting the period of an externally applied signal and a frequency divider circuit. This frequency divider circuit divides the frequency of the output signal from the VCO according to the period detected by the period-detecting circuit and feeds the resulting signal back to the VCO.

Abstract: The objective of this invention is to compensate or avoid the influence of offset in an easy and efficient manner, to correctly match the voltage of the output signal with the voltage of the input signal, that is, the target value, and to significantly reduce the current consumption. When voltage follower 32L supplies bias voltage VBn to each of constant current source circuits 58L, 60L, it acts as a source-type voltage follower. However, when the bias voltage applied to each of constant current source circuits 58L, 60L is changed from VBn to Vss of the power supply voltage level, each of constant current source circuits 58L, 60L is turned off, and no current flows through them. When the constant current source circuit 58 is turned off in differential input part 44L, the potential at the output terminal (node) NL rises almost to the level of the power supply voltage Vdd. In this way, the driving transistor 62L is also turned off in output part 46L.

Abstract: A LSI includes a logic circuit, a PLL circuit and a built-in self-test (BIST) circuit. When the PLL circuit detects a phase lock of the system clock signal of the LSI with a reference clock signal under the condition of presence of a test instruction signal, the PLL delivers a test enable signal to the BIST circuit. The BIST circuit responds to the test enable signal to test the logic circuit in a functional test. The BIST circuit transmits the test result data to an IC tester after the functional test. Throughput of the functional test can be improved by eliminating transmission of the test enable signal from the IC tester to the LSI.

Abstract: A semiconductor having multi-layer metalization which has a metal layer between aluminum alloy and metal nitride layers, that prevents failure of interconnects when electromigration causes a discontinuity in the aluminum alloy layer. In a one embodiment, the metal of the metal layer and the metal of the nitride layer are both the same metal, such as titanium. In a method of manufacturing the semiconductor device, an insulating layer is formed on a surface of a semiconductor substrate, and in vacuum chambers, the alloy layer is-formed on the insulating layer, a metal layer is formed on the alloy layer, and a metal nitride layer is formed on the metal layer in an nitrogen atmosphere. Sputtering, such as RF-bias sputtering, or thermal evaporation deposition, may be used to apply the respective nitride, metal and alloy layers.

Abstract: When a semiconductor integrated device is in an inactive state without being supplied with electric power, depletion type NMOS transistors act as resistors whereby a signal line connected to an input pad is electrically connected to the sources of input transistors via the NMOS transistors. In this situation, if an electrostatic surge is applied to the input pad, the surge is released to a voltage supply line. This ensures that the semiconductor integrated device is prevented from being damaged by the electrostatic surge. When electric power is supplied to the semiconductor integrated device and it becomes active, the NMOS transistors come to behave as insulating elements and thus these NMOS transistors have no adverse effects on the normal operation of the semiconductor integrated device.

Abstract: A phase locked loop makes a system clock signal synchronous to a horizontal synchronizing signal for a display unit, and a lock-in detecting circuit monitors said phase locked loop to see whether or not a phase difference takes place between the system clock signal and the horizontal synchronizing signal, wherein the lock-in detecting circuit measures the unlocked state between the system clock signal and the horizontal synchronizing signal in a window defined in a vertical synchronizing period and, thereafter, compares the time period of the unlocked state with a critical value to see whether or not the unlocked state is due to a temporary phenomenon or a phase difference to be corrected so that an detecting signal of the lock-in detecting circuit is reliable.

Abstract: The present invention offers a tracheal smooth muscle relaxant containing the compound represented by the following formula (1) or pharmacologically acceptable salt thereof as an effective ingredient.

Abstract: The present invention relates to a semiconductor device which utilizes a first conduction MOS output transistor 11 as an output transistor. The inventive semiconductor device have a advantage that the occupied area of an electrostatic breakdown preventing circuit is smaller than that of the conventional device, and the resistance against the electrostatic breakdown is better than that of the conventional device, and further an additional manufacturing process is not required, thereby obtaining the semiconductor device with an improved resistance. The inventive device is formed that a second conduction MOS transistor 13 functions as an electrostatic breakdown preventing circuit, with a drain of which being connected to an output terminal 15, and connected in a parallel form with the output transistor.

Abstract: The transistor protection device provides a circuit capable of obtaining a sufficient discharge characteristic when an electrostatic discharge voltage is applied to a semiconductor integrated circuit composed of a bipolar transistor. The protection device is provided across an emitter-base (E-B) junction of the bipolar transistor. When an electrostatic discharge voltage for biasing the E-B junction in the reverse direction is applied, the protection device is turned on and the surge current flows through the protection device such that the current which flows into the E-B junction of the transistor is greatly reduced so as to prevent electrostatic breakdown.

Abstract: A semiconductor having multi-layer metalization which has a metal layer between aluminum alloy and metal nitride layers, that prevents failure of interconnects when electromigration causes a discontinuity in the aluminum alloy layer. In a one embodiment, the metal of the metal layer and the metal of the nitride layer are both the same metal, such as titanium. In a method of manufacturing the semiconductor device, an insulating layer is formed on a surface of a semiconductor substrate, and in vacuum chambers, the alloy layer is formed on the insulating layer, a metal layer is formed on the alloy layer, and a metal nitride layer is formed on the metal layer in an nitrogen atmosphere. Sputtering, such as DC magnetron sputtering, RF-bias sputtering, or thermal evaporation deposition, may be used to apply the respective nitride, metal and alloy layers.

Abstract: A semiconductor integrated circuit includes an internal circuit, and ground and power supply lines for activating the internal circuit. An output MISFET is activated by peripheral circuit ground and power supply lines. For protection of the internal circuit from the effects of ground or power supply line noise, an impedance electrically separates the power supply lines for the internal and peripheral circuits and/or the ground lines for the peripheral and internal circuits. A surge protection circuit is provided between the gate of the output MISFET, and either or both of the ground and power supply lines for the peripheral circuitry.

Abstract: In an input/output protection circuit, since the drain of an input protection MOS transistor is directly connected to the cathode of input protection diode and the source and gate of the input protection MOS transistor and the anode of the input protection diode are respectively grounded, an excessive voltage supplied from an external electrode is received by the cathode of the input protection diode and the drain of the input protection MOS transistor before it reaches the internal circuit of a semiconductor device, so that the input/output protection circuit is free from the increase of junction capacitance due to the pattern of the input protection diode. Moreover, when an excessive voltage is input to the device, the input protection diode breaks down prior thereto so as to reduce the voltage at which the input protection MOS transistor starts to conduct. As a result, a high-speed and certain input protection is realized.

Abstract: In order to prevent the occurrence of corrosion due to the sliding of a relatively wide aluminum conductive layer (12) such as a power source conductive layer or a ground conductive layer, formed on a semiconductor substrate (11), breakage of a lower conductive layer due to the sliding of an upper aluminum conductive layer (12) in case of a multilayer interconnection, and the creation of voids in the lower aluminum conductive layer due to the moisture beneath the relatively wide metal conductive layer in case of a multi layer interconnection etc., the conductive layer structure is constructed so that the conductive layer (12) relatively great in width is divided into several conductive layer portions and so that the width of each of the divided conductive layer portions is in a range of 10 .mu.m to 40 .mu.m.

Abstract: In a semiconductor device having an external input terminal, a first insulated-gate field-effect transistor formed on a semiconductor substrate, and having a gate connected to the input terminal, and a second insulated-gate field effect transistor having a drain connected to the gate of the first insulated-gate field-effect transistor, and having a gate and source connected to a reference voltage source, the ratio W/L of the channel width W to the channel length L of the second insulated-gate field effect transistor is not less than 12.

Abstract: In a semiconductor device having an external input terminal, a first insulated-gate field-effect transistor formed on a semiconductor substrate, and having a gate connected to the input terminal, and a second insulated-gate field effect transistor having a drain connected to the gate of the first insulated-gate field-effect transistor, and having a gate and source connected to a reference voltage source, the ratio W/L of the channel width W to the channel length L of the second insulated-gate field effect transistor is not less than 12.

Abstract: A method of testing the susceptibility of a semiconductor device having a dielectric package to withstand electrostatic charges charged on the dielectric package, comprising the steps of: connecting a switch in between input/output terminals of the semiconductor device and a reference potential source, applying a prescribed potential to the surface of the dielectric package to charge the surface with electric charges while the switch is in an open state, applying a prescribed potential to a terminal of the semiconductor device via a resistor, and discharging the charges to the reference potential source by closing the switch.

Abstract: A method and apparatus for examining the susceptibility of a semiconductor device to damage by discharge of electrostatic charge on a dielectric package of the device. The package is electrically charged, with an input or output pin of the device disconnected at least from a reference potential of the charging source. The input or output pin is then connected to the reference potential through a load impedance with the charging continued, to effect discharging of the charge on the package. Thus, the electrostatic breakdown voltage of the device can be determined with accuracy by testing of the device after each charging and discharging operation at successively higher charging potentials.