Patents by Inventor Yasumori Fukushima
Yasumori Fukushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8354329Abstract: A method for manufacturing a semiconductor device includes: a first step of forming a base layer, which includes an element portion having a gate electrode and a flat interlayer insulating film formed so as to cover the gate electrode; a second step of ion implanting a delamination material into the base layer to form a delamination layer; a third step of bonding the base layer to a substrate; and a fourth step of separating and removing a part of the base layer along the delamination layer. An implantation depth of the delamination material in the gate electrode is substantially the same as that of the delamination material in the interlayer insulating film.Type: GrantFiled: November 14, 2008Date of Patent: January 15, 2013Assignee: Sharp Kabushiki KaishaInventors: Michiko Takei, Yasumori Fukushima, Kazuhide Tomiyasu, Masao Moriguchi, Yutaka Takafuji
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Publication number: 20130009302Abstract: A semiconductor device (130) including: a bonding substrate (100); a thin film element (80) formed on the bonding substrate (100); and a semiconductor element (90a) bonded to the bonding substrate (100), the semiconductor element including a semiconductor element main body (50) and a plurality of underlying layers (51-54) stacked on a side of the semiconductor element main body facing the bonding substrate (100), wherein the underlying layer (54) closest to the bonding substrate (100) includes an extended section (E) formed by extending the circuit pattern toward the thin film element (80), a resin layer (120) is provided between the thin film element (80) and the semiconductor element (90a), and the thin film element (80) is connected to the semiconductor element main body (50) via a connection line (121a) provided on the resin layer (120), the extended section (E), and the circuit patterns.Type: ApplicationFiled: December 2, 2010Publication date: January 10, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kenshi Tada, Shin Matsumoto
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Publication number: 20120326264Abstract: A method of fabricating a semiconductor device of the present invention includes the steps of forming a single crystal semiconductor device, attaching the single crystal semiconductor device on a substrate, forming a TFT on a glass substrate, and electrically connecting the single crystal semiconductor device and the TFT. In the step of forming a single crystal semiconductor device, an alignment mark is provided at the single crystal semiconductor device. In the step of attaching a single crystal semiconductor device, the single crystal semiconductor device is positioned and attached on the glass substrate based on the machining accuracy of an attachment device. In the step of forming a TFT, the TFT is positioned and provided on the glass substrate based on the alignment mark provided at the single crystal semiconductor device.Type: ApplicationFiled: May 18, 2010Publication date: December 27, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Yasumori Fukushima, Yutaka Takafuji, Kenshi Tada
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Patent number: 8293621Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.Type: GrantFiled: June 1, 2011Date of Patent: October 23, 2012Assignee: Sharp Kabushiki KaishaInventors: Yutaka Takafuji, Yasumori Fukushima, Masao Moriguchi
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Publication number: 20120262660Abstract: An organic EL display device (1) includes an organic substrate (2) and an organic EL display element (11) provided on the organic substrate (2). A honeycomb-shaped structural element (30) including a plurality of cells (30b) separated from each other by a cell wall (30a) is provided on a surface opposite to the organic EL display element (11) of the organic substrate (2).Type: ApplicationFiled: March 28, 2011Publication date: October 18, 2012Applicant: Sharp Kabushiki KaishaInventors: Masaki Fujiwara, Yasumori Fukushima
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Patent number: 8288184Abstract: A production method for producing a semiconductor device capable of improving surface flatness and suppressing a variation in electrical characteristics of the semiconductor chip, and improving production yield. The production method includes the steps of: forming a first insulating film on a semiconductor substrate and on a conductive pattern film formed on the semiconductor substrate and reducing a thickness of the first insulating film in a region where the conductive pattern film is arranged by patterning; forming a second insulating film and polishing the second insulating film, thereby forming a flattening film; implanting a substance for cleavage into the semiconductor substrate through the flattening film, thereby forming a cleavage layer; transferring the semiconductor chip onto a substrate with an insulating surface so that the chip surface on the side opposite to the semiconductor substrate is attached thereto; and separating the semiconductor substrate from the cleavage layer.Type: GrantFiled: October 14, 2008Date of Patent: October 16, 2012Assignee: Sharp Kabushiki KaishaInventors: Michiko Takei, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Steven Roy Droes
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Patent number: 8207046Abstract: To prevent bubbles from occurring along a transfer interface, the present method includes the steps of: forming a peeled layer 10 in a transferred member 6 by implanting a peeled-layer forming substance into the transferred member 6; forming a planar surface in the transferred member 6 by planarizing a surface of the transferred member 6; forming a composite including the transferred member 6 and a glass substrate 2 by directly combining the transferred member 6 via the planar surface with a surface of the glass substrate 2; and peeling a part of the transferred member 6 from the composite along the peeled layer 10 serving as an interface by heat-treating the composite.Type: GrantFiled: October 21, 2008Date of Patent: June 26, 2012Assignee: Sharp Kabushiki KaishaInventors: Michiko Takei, Shin Matsumoto, Yasumori Fukushima, Yutaka Takafuji
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Publication number: 20120155038Abstract: The present invention provides a high-performance flexible circuit board having excellent flexibility, a fine wiring pattern, and fine electric contacts, and a manufacturing method thereof. In a flexible circuit board (20), a second insulating layer (24) made of an inorganic material is positioned between a wiring layer (25) and a first insulating layer (23) made of an inorganic material.Type: ApplicationFiled: July 28, 2010Publication date: June 21, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Yasumori Fukushima, Masaki Fujiwara, Steven Roy Droes
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Patent number: 8188564Abstract: A method for manufacturing a semiconductor device including a thin film device unit including a TFT, and a peripheral device unit provided around the thin film device unit and including a semiconductor element, includes a first step of preparing a substrate, a second step of bonding the peripheral device unit directly to the substrate, and a third step of forming the thin film device unit on the substrate to which the peripheral device unit is bonded.Type: GrantFiled: July 24, 2008Date of Patent: May 29, 2012Assignee: Sharp Kabushiki KaishaInventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kazuo Nakagawa
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Publication number: 20120038022Abstract: Disclosed is a glass substrate (20) that is capable of constituting a semiconductor device (10) when a monocrystalline silicon thin film (90) is provided on the surface of the substrate by transfer. The surface of the glass substrate (20) has a receiving surface (22) onto which the monocrystalline silicon thin film (90) can be provided. The height of the ripples on the receiving surface (22) having a period of 200 to 500 microns is no more than 0.40 nm.Type: ApplicationFiled: October 26, 2009Publication date: February 16, 2012Applicant: SHARP KABUSHIKI KAISHAInventors: Kazuhide Tomiyasu, Yutaka Takafuji, Yasumori Fukushima, Kazuo Nakagawa, Kenshi Tada, Michiko Takei, Shin Matsumoto
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Patent number: 8101502Abstract: A device portion forming step includes an assisting layer forming step of forming a planarization assisting layer, which covers a plurality of conductive films, over a first planarizing layer before forming a second planarizing layer. In the assisting layer forming step, the planarization assisting layer is formed so that a height of the planarization assisting layer from a surface of the first planarizing layer located on a side opposite to the substrate layer becomes equal between at least a part of a region where the conductive films are formed, and at least a part of a region where no conductive film is formed.Type: GrantFiled: April 1, 2008Date of Patent: January 24, 2012Assignee: Sharp Kabushiki KaishaInventors: Yasumori Fukushima, Yutaka Takafuji, Kazuhide Tomiyasu, Michiko Takei, Steven Droes
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Publication number: 20110309467Abstract: Disclosed is a semiconductor device including a substrate for bonding (10a), and a semiconductor element part (25aa) which is bonded to the substrate (10a), and in which an element pattern (T) is formed, wherein in a bonded interface between the substrate (10a) and the semiconductor element part (25aa), recessed portions (23a) are formed in at least one of the substrate (10a) and the semiconductor element part (25aa).Type: ApplicationFiled: November 25, 2009Publication date: December 22, 2011Applicant: SHARP KABUSHIKI KAISHAInventors: Shin Matsumoto, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Kenshi Tada
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Publication number: 20110278678Abstract: This invention provides a semiconductor device having a semiconductor element that has low-resistance and a stable contact connection, even when the wiring is connected from the side of the single-crystal silicon layer on which the impurity concentration is lower. This invention provides a semiconductor device comprising, on a substrate, a semiconductor device having a single-crystal semiconductor film and a wiring connected to the single-crystal semiconductor film, and in the single-crystal semiconductor film, an impurity concentration on one surface side is different from an impurity concentration on another surface side, the wiring being connected to the surface side on which the impurity concentration is lower, the resistivity of a region of the single-crystal semiconductor film to which the wiring is connected being no less than 1 ??cm and no more than 0.01 ?cm.Type: ApplicationFiled: December 17, 2009Publication date: November 17, 2011Applicant: SHARP KABUSHIKI KAISHAInventors: Yasumori Fukushima, Yutaka Takafuji
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Publication number: 20110272694Abstract: The present invention is intended to provide a glass substrate (20), made of an insulating material, which can constitute a semiconductor apparatus (10) by transferring a single crystal silicon film (50) or a substrate including a semiconductor device onto a surface (24) of the insulating substrate, a transferred surface (26) being part of the surface (24), the single crystal silicon film (50) capable of being provided on the transferred surface (26), and the transferred surface (26) having an arithmetic mean roughness of not more than 0.4 nm.Type: ApplicationFiled: September 8, 2008Publication date: November 10, 2011Inventors: Michiko Takei, Shin Matsumoto, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
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Publication number: 20110269284Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.Type: ApplicationFiled: June 1, 2011Publication date: November 3, 2011Applicant: SHARP KABUSHIKI KAISHAInventors: Yutaka Takafuji, Yasumori Fukushima, Masao Moriguchi
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Publication number: 20110241174Abstract: Provided is a semiconductor device manufacturing method wherein the following steps are performed; a step of forming at least a part of an element on a base body layer, a step of forming a peeling layer, a step of forming a planarizing film; a step of forming a die by separating the base body layer at a separating region; a step of bonding the die to a substrate by bonding the die on the planarizing film; and a step of peeling and removing a part of the base body layer along the peeling layer. Prior to the step of forming the die, a step of forming a groove opened on the surface of the planarizing film such that at least a part of the separating region is included on the bottom surface of the groove, and forming the die such that the die has a polygonal outer shape wherein all the internal angles are obtuse by forming the groove is performed.Type: ApplicationFiled: August 21, 2009Publication date: October 6, 2011Applicant: SHARP KABUSHIKI KAISHAInventors: Michiko Takei, Yasumori Fukushima, Kazuhide Tomiyasu, Shin Matsumoto, Kazuo Nakagawa, Yutaka Takafuji
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Patent number: 8017492Abstract: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.Type: GrantFiled: August 12, 2008Date of Patent: September 13, 2011Assignee: Sharp Kabushiki KaishaInventors: Yasumori Fukushima, Masao Moriguchi, Yutaka Takafuji
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Patent number: 8008205Abstract: A method of the present invention includes a first planarization film formation step of forming, in at least part of a flat portion of the second regions, a first planarization film so as to have a uniform thickness; a second planarization film formation step of forming a second planarization film between the first planarization films to be coplanar with a surface of the first planarization film; a peeling layer formation step of forming a peeling layer by ion implantation of a peeling material into the base layer via the first planarization film or the second planarization film; and a separation step of separating part of the base layer along the peeling layer.Type: GrantFiled: October 13, 2006Date of Patent: August 30, 2011Assignee: Sharp Kabushiki KaishaInventors: Yasumori Fukushima, Yutaka Takafuji, Michiko Takei, Kazuhide Tomiyasu
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Patent number: 7989304Abstract: A transistor formed on a monocrystalline Si wafer is temporarily transferred onto a first temporary supporting substrate. The first temporarily supporting substrate is heat-treated at high heat so as to repair crystal defects generated in a transistor channel of the monocrystalline Si wafer when transferring the transistor. The transistor is then made into a chip and transferred onto a TFT substrate. In order to transfer the transistor which has been once separated from the monocrystalline Si wafer, a different method from a stripping method utilizing ion doping is employed.Type: GrantFiled: December 13, 2006Date of Patent: August 2, 2011Assignee: Sharp Kabushiki KaishaInventors: Michiko Takei, Kazuhide Tomiyasu, Yasumori Fukushima, Yutaka Takafuji
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Publication number: 20110042693Abstract: A semiconductor device (10) includes a support substrate (14), an adhered device part (11) adhered to the support substrate (14), a multilayer device part (13) stacked on the adhered device part (11), and an adjacent device part (12) formed in a region adjacent to the adhered device part on the support substrate (14). The adhered device part (11), the multilayer device part (13), and the adjacent device part (12) are electrically connected to one another.Type: ApplicationFiled: April 9, 2009Publication date: February 24, 2011Applicant: SHARP KABUSHIKI KAISHAInventors: Kenshi Tada, Yutaka Takafuji, Yasumori Fukushima, Kazuhide Tomiyasu, Michiko Takei, Kazuo Nakagawa, Shin Matsumoto