Patents by Inventor Yasumori Fukushima

Yasumori Fukushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6103600
    Abstract: A quantum dot and quantum fine wire forming method is provided which can allow control of the position for crystalline particle growth and enables formation of particles with high uniformity in size and density and with high reproducibility. After an Si substrate is formed with a step by a dry etching method, an SiO.sub.2 film is formed on the surface of the substrate. The interior of a reaction chamber is evacuated to a vacuum of 10.sup.-8 Torr, and then an Si.sub.2 H.sub.6 gas is introduced into the reaction chamber to flow therein so that Si crystal particles (quantum dots) are formed along the step. The step is formed by conventional photolithography and dry etching; therefore, the position for quantum dot growth can be easily controlled. By controlling the rate and time period of gas flow and the temperature of the substrate it is possible to form quantum fine wires, and to control the size of quantum dots and/or thickness of quantum fine wires.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: August 15, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Yasumori Fukushima, Kenta Nakamura
  • Patent number: 6090666
    Abstract: There are provided a method for fabricating semiconductor nanocrystals which are highly controllable and less variable in density and size, as well as a semiconductor memory device which, with the use of the semiconductor nanocrystals, allows thickness of a insulating film between nanocrystals and channel region to be easily controlled and involves less variations in characteristics such as threshold and programming performance, and which is fast reprogrammable and has nonvolatility. Under a low pressure below atmospheric pressure, an amorphous silicon thin film 3 is deposited on a tunnel insulating film 2 formed on a silicon substrate 1.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: July 18, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Kenta Nakamura, Yasumori Fukushima
  • Patent number: 6013922
    Abstract: A semiconductor storage element has a source region, a drain region, and a channel region connecting the source region with the drain region, which each are formed on an insulation film of a substrate. A gate insulation film is formed between the channel region and a gate electrode. The source region, the drain region, and the channel region consist of an aggregate of spherical grains which are arranged two-dimensionally on the insulation film and connected with one another such that the adjacent spherical grains are conductive to one another. The channel region contains at least one carrier trap region provided at a location other than an electric path thereof.
    Type: Grant
    Filed: May 28, 1998
    Date of Patent: January 11, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Ueda, Kenta Nakamura, Yasumori Fukushima