Patents by Inventor Yasuo Yamagishi
Yasuo Yamagishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20060012460Abstract: A conductive composition layer, conductive particles as a raw material, a conductive composition therefor, a manufacturing method of the conductive composition layer, etc. are provided wherewith heat conductance can be accelerated between electronic devices or electronic devices can be electrically connected. The conductive composition layer is formed by subjecting to heat treatment at a temperature lower than 230° C. a conductive composition comprising conductive particles having a metal base material and a metal coating material thereon as well as a thermosetting resin having a curing temperature that is lower than 230° C. and/or a thermoplastic resin having a melting point that is lower than 230° C.Type: ApplicationFiled: September 22, 2005Publication date: January 19, 2006Applicant: FUJITSU LIMITEDInventors: Kozo Shimizu, Yasuo Yamagishi
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Patent number: 6947625Abstract: The optical deflector comprises: an optical waveguide 12 of a dielectric material having electrooptical effect; and a pair of electrodes 10, 14 opposed to each other across the optical waveguide, an electric field is applied between the opposed electrodes to change a refractive index of the dielectric material to thereby control a propagating direction of signal light propagating in the optical waveguide 12, wherein the dielectric material has a first refractive index in its initial state, has a second refractive index by application of an electric field of a first polarity, and retains as a third refractive index a refractive index obtained after the electric field has been removed. The dielectric material has the third refractive index has the first refractive index by the application of an electric field of a second polarity different from the first polarity and removal of the electric field.Type: GrantFiled: January 14, 2005Date of Patent: September 20, 2005Assignee: Fujitsu LimitedInventors: Motoyuki Nishizawa, Masatoshi Ishii, Yasuo Yamagishi
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Patent number: 6943447Abstract: A thin film multi-layer wiring substrate comprising a plurality of wiring layers, each adjacent pair of wiring layers being separated by an insulating layer, wherein at least one of the wiring layers includes wiring formed by an inner conductor member and a conductor layer surrounding the periphery thereof through an insulating material.Type: GrantFiled: January 9, 2003Date of Patent: September 13, 2005Assignee: Fujitsu LimitedInventors: Yoshikatsu Ishizuki, Nobuyuki Hayashi, Masataka Mizukoshi, Yasuo Yamagishi
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Publication number: 20050179128Abstract: A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.Type: ApplicationFiled: April 13, 2005Publication date: August 18, 2005Applicant: Fujitsu LimitedInventors: Takeshi Shioga, John Baniecki, Kazuaki Kurihara, Yasuo Yamagishi
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Publication number: 20050123228Abstract: The optical deflector comprises: an optical waveguide 12 of a dielectric material having electrooptical effect; and a pair of electrodes 10, 14 opposed to each other across the optical waveguide, an electric field is applied between the opposed electrodes to change a refractive index of the dielectric material to thereby control a propagating direction of signal light propagating in the optical waveguide 12, wherein the dielectric material has a first refractive index in its initial state, has a second refractive index by application of an electric field of a first polarity, and retains as a third refractive index a refractive index obtained after the electric field has been removed. The dielectric material has the third refractive index has the first refractive index by the application of an electric field of a second polarity different from the first polarity and removal of the electric field.Type: ApplicationFiled: January 14, 2005Publication date: June 9, 2005Applicant: Fujitsu LimitedInventors: Motoyuki Nishizawa, Masatoshi Ishii, Yasuo Yamagishi
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Patent number: 6894396Abstract: A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.Type: GrantFiled: July 16, 2003Date of Patent: May 17, 2005Assignee: Fujitsu LimitedInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara, Yasuo Yamagishi
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Patent number: 6879739Abstract: An optical deflector including an optical waveguide of a dielectric material having electrooptical effect; and a pair of electrodes opposed to each other across the optical waveguide. An electric field is applied between the opposed electrodes to change a refractive index of the dielectric material to thereby control a propagating direction of signal light propagating in the optical waveguide, wherein the dielectric material has a first refractive index in its initial state, has a second refractive index by application of an electric field of a first polarity, and retains as a third refractive index a refractive index obtained after the electric field has been removed. The dielectric material having the third refractive index has the first refractive index by the application of an electric field of a second polarity different from the first polarity and removal of the electric field.Type: GrantFiled: February 26, 2002Date of Patent: April 12, 2005Assignee: Fujitsu LimitedInventors: Motoyuki Nishizawa, Masatoshi Ishii, Yasuo Yamagishi
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Publication number: 20050069274Abstract: An optoelectronic component is mounted at a precise position on a waveguide substrate so as to reduce loss in propagating light, and electrically connect electrodes on the waveguide substrate and the optoelectronic component. The waveguide substrate has an optical waveguide and a recessed portion for mounting the optoelectronic component, and electrodes are arranged on the recessed portion. A great number of globular elastic conductive particles are distributed on the bottom surface of the recessed portion. Thereafter, the optoelectronic component is placed in the recessed portion so as to press the globular elastic conductive particles, and alignment between the optical waveguide in the waveguide substrate and an optical waveguide in the optoelectronic component is adjusted. Then, the optoelectronic component is fixed to the waveguide substrate with an optical adhesive while the alignment is precisely adjusted.Type: ApplicationFiled: November 18, 2004Publication date: March 31, 2005Applicant: FUJITSU LIMITEDInventors: Tsuyoshi Aoki, Masayuki Kato, Yasuo Yamagishi, Tomoyuki Akahoshi, Nawalage Cooray, Mamoru Kurashina
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Publication number: 20050058399Abstract: An optical waveguide structure capable of optically coupling a surface type optical device, such as a surface emitting laser diode or a photodiode, and a transmission medium, such as an optical fiber, located so that their light output surface and light input surface will form an angle of about 90° with each other simply and easily. The optical waveguide structure comprises a first clad section having a curved surface for gradually turning the direction in which light travels almost squarely and a groove formed in the curved surface along the direction in which light travels, a core section which is made from a transparent material with a refractive index higher than the refractive index of the first clad section and with which the groove is filled in, and a second clad section which covers an exposed surface of the core section and the curved surface of the first clad section and which is integrated with the first clad section.Type: ApplicationFiled: September 10, 2004Publication date: March 17, 2005Applicant: FUJITSU LIMITEDInventors: Motoyuki Nishizawa, Koji Tsukamoto, Masayuki Kato, Yasuo Yamagishi
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Patent number: 6846549Abstract: A multilayer printed wiring board includes a core member having a plurality of glass clothes impregnated with a resin. Each of the glass clothes is woven with glass yarns each of which includes a bundle of glass filaments. One or more buildup layers are laminated on one or each surface of the core member. The core member has an elastic modulus which is no less than 100 times that of the buildup layer at 240° C.Type: GrantFiled: September 26, 2001Date of Patent: January 25, 2005Assignee: Fujitsu LimitedInventors: Motoaki Tani, Nobuyuki Hayashi, Hiroyuki Machida, Takeshi Ishitsuka, Yasuo Yamagishi
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Publication number: 20040239349Abstract: A probe card includes probes, a build-up interconnection layer having a multilayer interconnection structure therein and carrying the probes on a top surface in electrical connection with the multilayer interconnection structure, and a capacitor provided on the build-up interconnection layer in electrical connection with one of the probes via the multilayer interconnection structure, wherein the multilayer interconnection structure includes an inner via-contact in the vicinity of the probe and the capacitor is embedded in a resin insulation layer constituting the build-up layer.Type: ApplicationFiled: July 18, 2003Publication date: December 2, 2004Applicant: FUJITSU LIMITEDInventors: Yasuo Yamagishi, Takeshi Shioga, John David Baniecki, Kazuaki Kurihara
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Patent number: 6806118Abstract: An electrode connecting method of connecting a first electrode and a second electrode is disclosed. The respective bonding surfaces of the first and second electrodes are activated. Then, each of the first and second electrodes having the activated surfaces is coated with a coating member for maintaining an activated state. A solid state bond between the first electrode and the second electrode is formed by pressure welding the first electrode and the second electrode so that the first and second electrodes break through the coating members.Type: GrantFiled: January 21, 2003Date of Patent: October 19, 2004Assignee: Fujitsu LimitedInventors: Keishiro Okamoto, Masataka Mizukoshi, Yasuo Yamagishi
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Patent number: 6768205Abstract: The objective of the present invention is to provide a reliable thin-film circuit substrate or via formed substrate that is provided with minute via plugs at a fine pitch. The objective is served by forming an insulation layer that functions as an etching stopper on a Si substrate, and then via holes are formed in the Si substrate, using a semiconductor process, until the etching stopper layer is exposed. Further, a thin-film circuit is formed on the insulation layer, and the insulation layer is removed at the via holes such that the thin-film circuit is exposed. As necessary, the thin film circuit is heat-treated, and then the via holes are filled with an electrically conductive material and vamp electrodes are formed.Type: GrantFiled: March 1, 2002Date of Patent: July 27, 2004Assignee: Fujitsu LimitedInventors: Osamu Taniguchi, Tomoko Miyashita, Yasuo Yamagishi, Koji Omote, Yoshihiko Imanaka
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Publication number: 20040012085Abstract: A semiconductor device comprises a carrier substrate, an integrated circuit chip mounted on the carrier substrate via bumps, and a capacitor provided to stabilize operation of the integrated circuit chip at high frequencies. In the semiconductor device, the capacitor is electrically connected to pads on bottom of the integrated circuit chip, and the capacitor is provided to have a height on the carrier substrate that is smaller than or equal to a height of the bumps on the carrier substrate.Type: ApplicationFiled: July 16, 2003Publication date: January 22, 2004Applicant: FUJITSU LIMITEDInventors: Takeshi Shioga, John David Baniecki, Kazuaki Kurihara, Yasuo Yamagishi
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Publication number: 20040009666Abstract: A thin film multi-layer wiring substrate comprising a plurality of wiring layers, each adjacent pair of wiring layers being separated by an insulating layer, wherein at least one of the wiring layers includes wiring formed by an inner conductor member and a conductor layer surrounding the periphery thereof through an insulating material. A printed circuit board comprising a signal line conductor formed on a first insulating layer which selectively covers a first ground layer spreading on a substrate, shield walls extending across gaps on both sides of the signal line conductor, and conductively connected to the first ground layer, and a second ground layer conductively connected to the shield walls, stretching across gaps above the signal line conductor, and in which a plurality of openings having lengths and distances of equal to or less than one quarter of a frequency handled by the signal line conductor are formed, is also disclosed.Type: ApplicationFiled: January 9, 2003Publication date: January 15, 2004Applicant: FUJITSU LIMITEDInventors: Yoshikatsu Ishizuki, Nobuyuki Hayashi, Masataka Mizukoshi, Yasuo Yamagishi
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Patent number: 6662345Abstract: A thermal analysis in heating a print-circuit board in a reflowing furnace is simulated by a processor using data required for the design and thermal analysis of the printed-circuit board that carries solder-bonded components. The result of simulation indicates the possibility of existence of unmelted solder bonds heated at peak temperature below a predetermined lower limit and solder bonds heated at temperature above a predetermined upper limit. On the basis of the result, the components that are likely to be heated at inapplicable temperature are redesigned so that they can actually be heated at temperature in the predetermined range. The modification of design is displayed.Type: GrantFiled: May 28, 2002Date of Patent: December 9, 2003Assignee: Fujitsu LimitedInventors: Hiroki Uchida, Yasuo Yamagishi
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Publication number: 20030148593Abstract: An electrode connecting method of connecting a first electrode and a second electrode is disclosed. The respective bonding surfaces of the first and second electrodes are activated. Then, each of the first and second electrodes having the activated surfaces is coated with a coating member for maintaining an activated state. A solid state bond between the first electrode and the second electrode is formed by pressure welding the first electrode and the second electrode so that the first and second electrodes break through the coating members.Type: ApplicationFiled: January 21, 2003Publication date: August 7, 2003Applicant: FUJITSU LIMITEDInventors: Keishiro Okamoto, Masataka Mizukoshi, Yasuo Yamagishi
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Publication number: 20030137056Abstract: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.Type: ApplicationFiled: January 6, 2003Publication date: July 24, 2003Applicant: Fujitsu LimitedInventors: Osamu Taniguchi, Yasuo Yamagishi, Koji Omote
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Patent number: 6596094Abstract: A solder paste, includes a flux, a solder alloy particle scattered or mixed in the flux and including Sn and Zn as composition elements, and a metal particle scattered or mixed in the flux and including an element in the IB group in the periodic table as a composition element.Type: GrantFiled: November 27, 2001Date of Patent: July 22, 2003Assignee: Fujitsu LimitedInventors: Masayuki Ochiai, Yasuo Yamagishi, Hiroki Uchida, Masayuki Kitajima, Masakazu Takesue, Tadaaki Shono
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Publication number: 20030118262Abstract: The optical device comprises a first substrate 10 having a control circuit formed on; optical waveguide layer 40 formed above the first substrate and having a refractive index changed by electro-optic effect; and second substrates 14a, 14b having prism electrodes 18 for applying voltages to the optical waveguide layer. The control circuit and the prism electrodes are electrically connected to each other via columnar conductors 20. Even in a case where thermal expansion coefficients of the control substrate and of the light deflection substrates are very different from each other, the pins are flexed corresponding to eternal forces, whereby junction is protected from being damaged in the joining processing. Thus, the optical switch can be highly reliable.Type: ApplicationFiled: November 6, 2002Publication date: June 26, 2003Applicant: Fujitsu LimitedInventors: Tsuyoshi Aoki, Yasuo Yamagishi