Patents by Inventor Yasushi Oka
Yasushi Oka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11982825Abstract: According to one embodiment, a liquid crystal optical element includes a transparent substrate including a main surface, an alignment film disposed on the main surface, and a liquid crystal layer overlapping the alignment film and including a cholesteric liquid crystal including liquid crystal molecules stacked helically and an additive exhibiting a liquid crystalline property. In the liquid crystal layer, a reflective surface along which alignment directions of the liquid crystal molecules are identical is inclined with respect to the main surface.Type: GrantFiled: May 17, 2023Date of Patent: May 14, 2024Assignees: Japan Display Inc., Oaka UniversityInventors: Koichi Igeta, Shinichiro Oka, Yasushi Tomioka, Hiroyuki Yoshida
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Publication number: 20240121893Abstract: According to an aspect, a stretchable device includes: a resin base member; and a signal line and a strain gauge stacked on the resin base member. The resin base member includes: a plurality of bodies disposed separately from each other; and a plurality of hinges that couple the bodies while meandering. The hinges each include: a plurality of bends that bend and are disposed between the bodies; and a base that linearly extends to couple one of the bodies to a corresponding one of the bends. The signal line includes: a bend signal line stacked on the bends; and a base signal line stacked on the base. The base signal line has an occupied area per unit length in a length direction of the signal line larger than the bend signal line when viewed in a stacking direction in which the signal line is stacked on the resin base member.Type: ApplicationFiled: October 4, 2023Publication date: April 11, 2024Applicant: Japan Display Inc.Inventors: Takumi SANO, Masatomo HISHINUMA, Yasushi TOMIOKA, Akio MURAYAMA, Shinichiro OKA
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Publication number: 20140140133Abstract: To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device. A plurality of memory cells each configured by a memory transistor having a floating gate and a control transistor coupled in series to the memory transistor is arranged in an array in an X direction and in a Y direction on the main surface of a semiconductor substrate. Then, a bit wire that couples drain regions of the memory transistors of the memory cells arranged in the X direction is provided in the lowermost wiring layer of a multilayer wiring structure formed over the semiconductor substrate and the bit wire is arranged to cover the whole floating gate electrode.Type: ApplicationFiled: January 27, 2014Publication date: May 22, 2014Applicant: Renesas Electronics CorporationInventors: Hideaki YAMAKOSHI, Yasushi OKA, Daisuke OKADA
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Patent number: 8351255Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.Type: GrantFiled: May 11, 2012Date of Patent: January 8, 2013Assignee: Renesas Electronics COrporationInventors: Kazuyoshi Shiba, Yasushi Oka
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Patent number: 8325524Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.Type: GrantFiled: October 13, 2010Date of Patent: December 4, 2012Assignee: Renesas Electronics CorporationInventors: Yasushi Oka, Tadashi Omae, Takesada Akiba
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Publication number: 20120223376Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.Type: ApplicationFiled: May 11, 2012Publication date: September 6, 2012Inventors: Kazuyoshi Shiba, Yasushi Oka
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Patent number: 8189377Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.Type: GrantFiled: February 24, 2011Date of Patent: May 29, 2012Assignee: Renesas Electronics CorporationInventors: Kazuyoshi Shiba, Yasushi Oka
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Publication number: 20110233639Abstract: To improve performance of a semiconductor device having a nonvolatile memory. Further to improve reliability of the semiconductor device. Furthermore, to improve performance of a semiconductor device as well as improving reliability of the semiconductor device. A plurality of memory cells each configured by a memory transistor having a floating gate and a control transistor coupled in series to the memory transistor is arranged in an array in an X direction and in a Y direction on the main surface of a semiconductor substrate. Then, a bit wire that couples drain regions of the memory transistors of the memory cells arranged in the X direction is provided in the lowermost wiring layer of a multilayer wiring structure formed over the semiconductor substrate and the bit wire is arranged to cover the whole floating gate electrode.Type: ApplicationFiled: March 13, 2011Publication date: September 29, 2011Inventors: Hideaki YAMAKOSHI, Yasushi OKA, Daisuke OKADA
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Publication number: 20110147819Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.Type: ApplicationFiled: February 24, 2011Publication date: June 23, 2011Inventors: KAZUYOSHI SHIBA, YASUSHI OKA
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Patent number: 7940561Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.Type: GrantFiled: October 21, 2009Date of Patent: May 10, 2011Assignee: Renesas Electronics CorporationInventors: Kazuyoshi Shiba, Yasushi Oka
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Publication number: 20110024814Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.Type: ApplicationFiled: October 13, 2010Publication date: February 3, 2011Inventors: Yasushi OKA, Tadashi Omae, Takesada Akiba
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Patent number: 7839683Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.Type: GrantFiled: September 18, 2008Date of Patent: November 23, 2010Assignee: Renesas Electronics CorporationInventors: Yasushi Oka, Tadashi Omae, Takesada Akiba
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Publication number: 20100038693Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.Type: ApplicationFiled: October 21, 2009Publication date: February 18, 2010Inventors: Kazuyoshi SHIBA, Yasushi OKA
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Patent number: 7652917Abstract: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.Type: GrantFiled: October 29, 2008Date of Patent: January 26, 2010Assignee: Renesas Technology Corp.Inventors: Yasushi Oka, Kazuyoshi Shiba
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Patent number: 7639541Abstract: A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the first region and a second semiconductor region is formed in the second region. The memory cells each include a capacitance element, including the first conductor film and second region, an element for reading data, including the first conductor film and first regions, and a selection field effect transistor, including the second conductor film and first regions. A length of the first conductor film of the capacitance element is larger than a length of the first conductor film of the element for reading data. A word line of the memory cell is connected to the second semiconductor region.Type: GrantFiled: January 9, 2008Date of Patent: December 29, 2009Assignee: Renesas Technology Corp.Inventors: Kazuyoshi Shiba, Yasushi Oka
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Patent number: 7623371Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.Type: GrantFiled: May 2, 2007Date of Patent: November 24, 2009Assignee: Renesas Technology Corp.Inventors: Kazuyoshi Shiba, Yasushi Oka
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Publication number: 20090154253Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.Type: ApplicationFiled: November 13, 2008Publication date: June 18, 2009Inventors: Kazuyoshi SHIBA, Yasuhiro Taniguchi, Yasushi Oka
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Publication number: 20090080257Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.Type: ApplicationFiled: September 18, 2008Publication date: March 26, 2009Inventors: YASUSHI OKA, Tadashi Omae, Takesada Akiba
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Publication number: 20090059677Abstract: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.Type: ApplicationFiled: October 29, 2008Publication date: March 5, 2009Inventors: YASUSHI OKA, Kazuyoshi Shiba
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Patent number: 7466599Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.Type: GrantFiled: October 26, 2007Date of Patent: December 16, 2008Assignee: Renesas Technology Corp.Inventors: Kazuyoshi Shiba, Yasuhiro Taniguchi, Yasushi Oka