Patents by Inventor Yasushi Oka
Yasushi Oka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090154253Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.Type: ApplicationFiled: November 13, 2008Publication date: June 18, 2009Inventors: Kazuyoshi SHIBA, Yasuhiro Taniguchi, Yasushi Oka
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Publication number: 20090080257Abstract: The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.Type: ApplicationFiled: September 18, 2008Publication date: March 26, 2009Inventors: YASUSHI OKA, Tadashi Omae, Takesada Akiba
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Publication number: 20090059677Abstract: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.Type: ApplicationFiled: October 29, 2008Publication date: March 5, 2009Inventors: YASUSHI OKA, Kazuyoshi Shiba
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Patent number: 7466599Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.Type: GrantFiled: October 26, 2007Date of Patent: December 16, 2008Assignee: Renesas Technology Corp.Inventors: Kazuyoshi Shiba, Yasuhiro Taniguchi, Yasushi Oka
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Patent number: 7460396Abstract: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.Type: GrantFiled: September 7, 2006Date of Patent: December 2, 2008Assignee: Renesas Technology Corp.Inventors: Yasushi Oka, Kazuyoshi Shiba
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Publication number: 20080259682Abstract: A semiconductor device includes a circuit forming area and a memory area including memory cells, first and second wells, a first conductor film formed over both wells and a second conductor film formed over the first well. First semiconductor regions are formed in the first region and a second semiconductor region is formed in the second region. The memory cells each include a capacitance element, including the first conductor film and second region, an element for reading data, including the first conductor film and first regions, and a selection field effect transistor, including the second conductor film and first regions. A length of the first conductor film of the capacitance element is larger than a length of the first conductor film of the element for reading data. A word line of the memory cell is connected to the second semiconductor region.Type: ApplicationFiled: January 9, 2008Publication date: October 23, 2008Inventors: Kazuyoshi Shiba, Yasushi Oka
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Publication number: 20080211001Abstract: Provided is a semiconductor device having, over the main surface of a semiconductor substrate, a main circuit region and a memory cell array of a flash memory. The memory cell array has a floating gate electrode for accumulating charges of data, while the main circuit region has a gate electrode of MIS•FET constituting the main circuit. In the main circuit region, an insulating film made of a silicon nitride film is formed to cover the gate electrode, whereby miniaturization of elements in the main circuit region is not impaired. The memory cell array has no such insulating film. This means that the upper surface of the floating gate electrode is not contiguous to the insulating film but is covered directly with an interlayer insulating film. According to such a constitution, leakage of electrons from the floating gate electrode of the memory cell array can be suppressed or prevented and the flash memory thus obtained has improved data retention characteristics.Type: ApplicationFiled: January 13, 2008Publication date: September 4, 2008Inventors: Kazuyoshi Shiba, Hideyuki Yashima, Yasushi Oka
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Patent number: 7388777Abstract: A plurality of nonvolatile memory cells that constitute a nonvolatile memory are disposed in array form. Selection MIS•FETs for memory cell selection are electrically connected every bits. Each of the nonvolatile memory cells has a MIS•FET for writing data, a MIS•FET for reading data, and a capacitance section. Gate electrodes of the MIS•FETs and a capacitance electrode of the capacitance section are constituted of part of the same floating gate electrode. A control gate electrode of the nonvolatile memory cell is formed of part of an n well to which the capacitance electrode is opposite.Type: GrantFiled: January 11, 2006Date of Patent: June 17, 2008Assignee: Renesas Technology Corp.Inventors: Kazuyoshi Shiba, Yasushi Oka
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Publication number: 20080056011Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.Type: ApplicationFiled: October 26, 2007Publication date: March 6, 2008Inventors: Kazuyoshi Shiba, Yasuhiro Taniguchi, Yasushi Oka
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Publication number: 20070296020Abstract: p-type wells are provided within an n-type embedded well of a semiconductor substrate lying in an area for forming a flash memory, in a state of being isolated from one another. A capacitance section, a data write/erase charge injection/discharge section and a data read MIS•FET are disposed in each of the p-type wells. The capacitance section is disposed between the data write/erase charge injection/discharge section and the data read MIS•FET. In the data write/erase charge injection/discharge section, writing and erasing of data by an FN tunnel current at a channel entire surface are performed.Type: ApplicationFiled: May 2, 2007Publication date: December 27, 2007Inventors: Kazuyoshi SHIBA, Yasushi Oka
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Patent number: 7313026Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.Type: GrantFiled: August 19, 2005Date of Patent: December 25, 2007Assignee: Renesas Technology Corp.Inventors: Kazuyoshi Shiba, Yasuhiro Taniguchi, Yasushi Oka
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Publication number: 20070058441Abstract: In a data program/erase device of a nonvolatile memory cell, data are re-written by means of an FN tunnel current of an entire channel surface. In a buried n-well of a semiconductor substrate in a flash memory formation region, p wells are placed in the form isolated from each other. In each of the p wells, a capacitor portion, a capacitor portion for programming/erasing data and an MIS•FET for reading data are placed. In the capacitor portion for programming/erasing data, rewriting (programming and erasing) of data is performed by means of an FN tunnel current of an entire channel surface.Type: ApplicationFiled: September 7, 2006Publication date: March 15, 2007Inventors: Yasushi Oka, Kazuyoshi Shiba
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Publication number: 20060170035Abstract: A plurality of nonvolatile memory cells that constitute a nonvolatile memory are disposed in array form. Selection MIS•FETs for memory cell selection are electrically connected every bits. Each of the nonvolatile memory cells has a MIS•FET for writing data, a MIS•FET for reading data, and a capacitance section. Gate electrodes of the MIS•FETs and a capacitance electrode of the capacitance section are constituted of part of the same floating gate electrode. A control gate electrode of the nonvolatile memory cell is formed of part of an n well to which the capacitance electrode is opposite.Type: ApplicationFiled: January 11, 2006Publication date: August 3, 2006Inventors: Kazuyoshi Shiba, Yasushi Oka
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Publication number: 20060050566Abstract: Provided is a nonvolatile memory with less element deterioration and good data retaining properties. In a nonvolatile memory formed by the manufacturing steps of a complementary type MISFET without adding thereto another additional step, erasing of data is carried out by applying 9V to an n type well, 9V to a p type semiconductor region, and ?9V to another p type semiconductor region and setting the source and drain of data writing and erasing MISFETs and data reading MISFETs at open potential to emit electrons from a gate electrode to a p well by FN tunneling. At this time, by applying a negative voltage to the p well having a capacitive element formed thereover and applying a positive voltage to the p well having the MISFETs formed thereover, a potential difference necessary for data erasing operation can be secured at a voltage low enough not to cause gate breakage.Type: ApplicationFiled: August 19, 2005Publication date: March 9, 2006Inventors: Kazuyoshi Shiba, Yasuhiro Taniguchi, Yasushi Oka
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Patent number: 6914832Abstract: A semiconductor memory device includes a plurality of blocks, each of which includes a memory cell array, and outputs data signals and a redundancy signal. The semiconductor memory device further includes at least one first multiplexer which is coupled to the blocks, and selects one of the blocks, and a second multiplexer which performs redundancy processing based on the data signals and the redundancy signal which have undergone block selection by the first multiplexer.Type: GrantFiled: September 2, 2003Date of Patent: July 5, 2005Assignee: Fujitsu LimitedInventors: Andy Cheung, Yasushi Oka
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Patent number: 6760271Abstract: A semiconductor memory device includes a plurality of input/output terminals, a memory cell array which are divided into blocks respectively corresponding to the input/output terminals such that only one of the blocks corresponds to a given one of the input/output terminals, sense amplifiers, which are connected to the blocks at a side thereof, and amplify data of the memory cell array, switches which are respectively connected to the sense amplifiers, and signal lines, which connect the sense amplifiers to a corresponding one of the input/output terminals via the switches.Type: GrantFiled: March 19, 2001Date of Patent: July 6, 2004Assignee: Fujitsu LimitedInventors: Harunobu Nakagawa, Yasushi Oka
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Publication number: 20040085799Abstract: A semiconductor memory device includes a plurality of blocks, each of which includes a memory cell array, and outputs data signals and a redundancy signal. The semiconductor memory device further includes at least one first multiplexer which is coupled to the blocks, and selects one of the blocks, and a second multiplexer which performs redundancy processing based on the data signals and the redundancy signal which have undergone block selection by the first multiplexer.Type: ApplicationFiled: September 2, 2003Publication date: May 6, 2004Inventors: Andy Cheung, Yasushi Oka
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Publication number: 20020024870Abstract: A semiconductor memory device includes a plurality of input/output terminals, a memory cell array which are divided into blocks respectively corresponding to the input/output terminals such that only one of the blocks corresponds to a given one of the input/output terminals, sense amplifiers, which are connected to the blocks at a side thereof, and amplify data of the memory cell array, switches which are respectively connected to the sense amplifiers, and signal lines, which connect the sense amplifiers to a corresponding one of the input/output terminals via the switches.Type: ApplicationFiled: March 19, 2001Publication date: February 28, 2002Applicant: FUJITSU LIMITEDInventors: Harunobu Nakagawa, Yasushi Oka