Patents by Inventor Yasutoshi Okuno
Yasutoshi Okuno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210193816Abstract: The structure of a semiconductor device with dual silicide contact structures and a method of fabricating the semiconductor device are disclosed. A method of fabricating the semiconductor device includes forming first and second fin structures on a substrate, forming first and second epitaxial regions on the first and second fin structures, respectively, forming first and second contact openings on the first and second epitaxial regions, respectively, selectively forming an oxide capping layer on exposed surfaces of the second epitaxial region, selectively forming a first metal silicide layer on exposed surfaces of the first epitaxial region, removing the oxide capping layer, and forming first and second conductive regions on the metal silicide layer and on the exposed surfaces of the second epitaxial region, respectively. The first metal silicide layer includes a first metal. The first and second conductive regions includes a second metal different from the first metal.Type: ApplicationFiled: December 19, 2019Publication date: June 24, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Peng-Wei Chu, Ding-Kang Shih, Sung-Li Wang, Yasutoshi Okuno
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Patent number: 11037837Abstract: A method for forming an epitaxial source/drain structure in a semiconductor device includes providing a substrate having a plurality of fins extending from the substrate. In some embodiments, a liner layer is formed over the plurality of fins. The liner layer is patterned to expose a first group of fins of the plurality of fins in a first region. In some embodiments, a first epitaxial layer is formed over the exposed first group of fins and a barrier layer is formed over the first epitaxial layer. Thereafter, the patterned liner layer may be removed. In various examples, a second epitaxial layer is selectively formed over a second group of fins of the plurality of fins in a second region.Type: GrantFiled: August 8, 2019Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Cheng-Long Chen, Yasutoshi Okuno, Pang-Yen Tsai
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Patent number: 11031300Abstract: A method for manufacturing a semiconductor structure is provided. The method includes: receiving a substrate having a first epitaxy region in a first transistor of a first conductive type and a second epitaxy region in a second transistor of a second conductive type; introducing an agent onto the first epitaxy region and the second epitaxy region, wherein the agent is selectively deposited to the second epitaxy region; selectively depositing a first metal layer on the first epitaxy region; and depositing a second metal layer on the first epitaxy region and the second epitaxy region. A semiconductor structure according to the method is also provided.Type: GrantFiled: January 18, 2019Date of Patent: June 8, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Sung-Li Wang, Peng-Wei Chu, Yasutoshi Okuno
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Patent number: 11018012Abstract: A method of forming a semiconductor device includes forming a source/drain region on a substrate, depositing a metal-rich metal silicide layer on the source/drain region, depositing a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and forming a contact plug on the silicon-rich metal silicide layer. This disclosure also describes a semiconductor device including a fin structure on a substrate, a source/drain region on the fin structure, a metal-rich metal silicide layer on the source/drain region, a silicon-rich metal silicide layer on the metal-rich metal silicide layer, and a contact plug on the silicon-rich metal silicide layer.Type: GrantFiled: August 5, 2019Date of Patent: May 25, 2021Inventors: Sung-Li Wang, Yasutoshi Okuno, Shih-Chuan Chiu
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Patent number: 11018142Abstract: A memory cell includes a first and second pull up transistor, a first and second pass gate transistor and a metal contact. The first pull up transistor has a first active region extending in a first direction. The first pass gate transistor has a second active region extending in the first direction, and being separated from the first active region in a second direction. The second active region is adjacent to the first active region. The second pass gate transistor is coupled to the second pull up transistor. The metal contact extends in the second direction, and extends from the first active region to the second active region. The metal contact couples drains of the first pull up transistor and the first pass gate transistor. The first and second pass gate transistors and the first and second pull up transistors are part of a four transistor memory cell.Type: GrantFiled: June 28, 2019Date of Patent: May 25, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hidehiro Fujiwara, Hung-Jen Liao, Hsien-Yu Pan, Chih-Yu Lin, Yen-Huei Chen, Yasutoshi Okuno
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Publication number: 20210151434Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over a substrate. The semiconductor device further includes an isolation region covering the semiconductor layer and nanostructures formed over the semiconductor layer. The semiconductor layer further includes a gate stack wrapping around the nanostructures. In addition, the isolation region is interposed between the semiconductor layer and the gate stack.Type: ApplicationFiled: January 4, 2021Publication date: May 20, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Winnie Victoria Wei-Ning CHEN, Meng-Hsuan HSIAO, Tung-Ying LEE, Pang-Yen TSAI, Yasutoshi OKUNO
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Patent number: 10998241Abstract: A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.Type: GrantFiled: June 27, 2019Date of Patent: May 4, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Mrunal A. Khaderbad, Pang-Yen Tsai, Yasutoshi Okuno
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Patent number: 10978354Abstract: A semiconductor device and a method of making the same are provided. A method according to the present disclosure includes forming a first type epitaxial layer over a second type source/drain feature of a second type transistor, forming a second type epitaxial layer over a first type source/drain feature of a first type transistor, selectively depositing a first metal over the first type epitaxial layer to form a first metal layer while the first metal is substantially not deposited over the second type epitaxial layer over the first type source/drain feature, and depositing a second metal over the first metal layer and the second type epitaxial layer to form a second metal layer.Type: GrantFiled: March 15, 2019Date of Patent: April 13, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Peng-Wei Chu, Sung-Li Wang, Yasutoshi Okuno
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Publication number: 20210104431Abstract: A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.Type: ApplicationFiled: November 23, 2020Publication date: April 8, 2021Inventors: Mrunal A. Khaderbad, Yasutoshi Okuno, Sung-Li Wang, Pang-Yen Tsai, Shen-Nan Lee, Teng-Chun Tsai
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Patent number: 10964542Abstract: A method includes removing a dummy gate stack to form an opening between gate spacers, selectively forming an inhibitor film on sidewalls of the gate spacers, with the sidewalls of the gate spacers facing the opening, and selectively forming a dielectric layer over a surface of a semiconductor region. The inhibitor film inhibits growth of the dielectric layer on the inhibitor film. The method further includes removing the inhibitor film, and forming a replacement gate electrode in a remaining portion of the opening.Type: GrantFiled: September 19, 2019Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yasutoshi Okuno, Teng-Chun Tsai, Ziwei Fang, Fu-Ting Yen
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Publication number: 20210091182Abstract: A semiconductor device includes a first semiconductor fin, a first epitaxial layer, a first alloy layer and a contact plug. The first semiconductor fin is on a substrate. The first epitaxial layer is on the first semiconductor fin. The first alloy layer is on the first epitaxial layer. The first alloy layer is made of one or more Group IV elements and one or more metal elements, and the first alloy layer comprises a first sidewall and a second sidewall extending downwardly from a bottom of the first sidewall along a direction non-parallel to the first sidewall. The contact plug is in contact with the first and second sidewalls of the first alloy layer.Type: ApplicationFiled: November 30, 2020Publication date: March 25, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-Li WANG, Mrunal A. KHADERBAD, Yasutoshi OKUNO
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Publication number: 20210082773Abstract: A method includes etching a hybrid substrate to form a recess in the hybrid substrate, in which the hybrid substrate includes a first semiconductor layer, a dielectric layer over the first semiconductor layer, and a second semiconductor layer over the first semiconductor layer, in which after the etching, a top surface of the first semiconductor layer is exposed to the recess; forming a spacer on a sidewall of the recess, in which the spacer is slanted at a first angle relative to a top surface of the first semiconductor layer; reshaping the spacer such that the a first sidewall of the reshaped spacer is slanted at a second angle relative to the top surface of the first semiconductor layer, in which the second angle is greater than the first angle; and performing a first epitaxy process to grow an epitaxy semiconductor layer in the recess after reshaping the spacer.Type: ApplicationFiled: November 13, 2020Publication date: March 18, 2021Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pei-Wei Lee, Tsung-Yu Hung, Pang-Yen Tsai, Yasutoshi Okuno
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Publication number: 20210066499Abstract: In an embodiment, a device includes: a semiconductor substrate having a channel region; a gate stack over the channel region; and an epitaxial source/drain region adjacent the gate stack, the epitaxial source/drain region including: a main portion in the semiconductor substrate, the main portion including a semiconductor material doped with gallium, a first concentration of gallium in the main portion being less than the solid solubility of gallium in the semiconductor material; and a finishing portion over the main portion, the finishing portion doped with gallium, a second concentration of gallium in the finishing portion being greater than the solid solubility of gallium in the semiconductor material.Type: ApplicationFiled: March 2, 2020Publication date: March 4, 2021Inventors: Martin Christopher Holland, Blandine Duriez, Marcus Johannes Henricus van Dal, Yasutoshi Okuno
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Publication number: 20210013146Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.Type: ApplicationFiled: September 29, 2020Publication date: January 14, 2021Inventors: Sung-Li Wang, Yasutoshi Okuno
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Patent number: 10886270Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer. The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.Type: GrantFiled: June 24, 2020Date of Patent: January 5, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
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Patent number: 10879117Abstract: The present disclosure describes a method of forming a replacement contact. For example, the replacement contact can include a metal with one or more first sidewall surfaces and a top surface. A first dielectric can be formed to abut the one or more first sidewall surfaces of the metal. A second dielectric can be formed over the first dielectric and the top surface of the metal. An opening in the second dielectric can be formed. A metal oxide structure can be selectively grown on the top surface of the metal, where the metal oxide structure has one or more second sidewall surfaces. One or more spacers can be formed to abut the one or more second sidewall surfaces of the metal oxide structure. Further, the metal oxide structure can be removed.Type: GrantFiled: April 8, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yee-Chia Yeo, Teng-Chun Tsai, Yasutoshi Okuno
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Publication number: 20200395216Abstract: A semiconductor device includes first and second semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins respectively includes a first channel region and a second channel region, which the first and second gate structures are respectively on. The first gate structure includes a first silicon oxide layer on the first channel region, a first high-k dielectric layer on the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer. The second gate structure includes a second silicon oxide layer on the second channel region, a second high-k dielectric layer on the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer. The first silicon oxide layer has a Si4+ ion concentration greater than a Si4+ ion concentration of a bottom portion of the second silicon oxide layer.Type: ApplicationFiled: August 31, 2020Publication date: December 17, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Andrew Joseph KELLY, Yusuke ONIKI, Yasutoshi OKUNO, Ta-Chun MA
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Patent number: 10868009Abstract: A method for forming a semiconductor device is provided. The method includes forming a first recess in a substrate. The method includes forming a first semiconductor layer into the first recess. The first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is lower than a second top surface of the substrate. The method includes forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the first top surface is substantially level with the second top surface of the substrate, and the second semiconductor layer and the substrate are made of different materials. The method includes forming a third semiconductor layer over the second semiconductor layer. The third semiconductor layer and the second semiconductor layer are made of different materials.Type: GrantFiled: March 4, 2020Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
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Patent number: 10867905Abstract: Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.Type: GrantFiled: May 31, 2018Date of Patent: December 15, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sung-Li Wang, Yasutoshi Okuno
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Patent number: 10854716Abstract: A semiconductor device includes a first semiconductor fin, a first epitaxial layer, a first alloy layer and a contact plug. The first semiconductor fin is on a substrate. The first epitaxial layer is on the first semiconductor fin. The first alloy layer is on the first epitaxial layer. The first alloy layer is made of one or more Group IV elements and one or more metal elements, and the first alloy layer comprises a first sidewall and a second sidewall extending downwardly from a bottom of the first sidewall along a direction non-parallel to the first sidewall. The contact plug is in contact with the first and second sidewalls of the first alloy layer.Type: GrantFiled: January 18, 2019Date of Patent: December 1, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-Li Wang, Mrunal A. Khaderbad, Yasutoshi Okuno