Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.

Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

Abstract: The present disclosure is generally related to semiconductor devices, and more particularly to a dielectric material formed in semiconductor devices. The present disclosure provides methods for forming a dielectric material layer by a cyclic spin-on coating process. In an embodiment, a method of forming a dielectric material on a substrate includes spin-coating a first portion of a dielectric material on a substrate, curing the first portion of the dielectric material on the substrate, spin-coating a second portion of the dielectric material on the substrate, and thermal annealing the dielectric material to form an annealed dielectric material on the substrate.

Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).

Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).

Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.

Abstract: A window frame measuring method is provided and includes the steps of: providing a smart electronic device having a window frame measuring application; starting the window frame measuring application of the smart electronic device to allow the image capturing unit to capture a code and a window frame externally and generate a code data and a window frame graphic data, respectively, which are then transmitted to the window frame measuring application by the transmission unit; analyzing and comparing the code data and the window frame graphic data by the window frame measuring application so as to generate a measuring data corresponding to dimensions of the window frame and transmit the measuring data to the display unit for display. Therefore, the window frame measuring method not only enables a user to perform smart human-machine interface interaction but also enhances accuracy in measurement of actual dimensions of window frames.

Abstract: A window frame measuring method is provided and includes the steps of: providing a smart electronic device having a window frame measuring application; starting the window frame measuring application of the smart electronic device to allow the image capturing unit to capture a code and a window frame externally and generate a code data and a window frame graphic data, respectively, which are then transmitted to the window frame measuring application by the transmission unit; analyzing and comparing the code data and the window frame graphic data by the window frame measuring application so as to generate a measuring data corresponding to dimensions of the window frame and transmit the measuring data to the display unit for display. Therefore, the window frame measuring method not only enables a user to perform smart human-machine interface interaction but also enhances accuracy in measurement of actual dimensions of window frames.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).

Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

Abstract: A device having an epitaxial region and dual metal-semiconductor alloy surfaces is provided. The epitaxial region includes an upward facing facet and a downward facing facet. The upward facing facet has a first metal-semiconductor alloy surface and the downward facing facet has a second metal-semiconductor alloy surface, wherein the first metal-semiconductor alloy is different than the second metal-semiconductor alloy.

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.

Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.

Abstract: FinFET structures and methods of forming the same are disclosed. In a method, a recess is formed exposing a plurality of semiconductor fins on a wafer. A dummy contact material is formed in the recess. The dummy contact material contains carbon. The dummy contact material is cured with one or more baking steps. The one or more baking steps harden the dummy contact material. A first portion of the dummy contact material is replaced with an inter-layer dielectric. A second portion of the dummy contact material is replaced with a plurality of contacts. The plurality of contacts are electrically coupled to source/drain regions of the plurality of semiconductor fins.

Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.